^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DA850/OMAP-L138 chip specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Derived from: arch/arm/mach-davinci/da830.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Original Copyrights follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 2009 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irqchip/irq-davinci-cp-intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/da8xx-cfgchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/clk-da8xx-cfgchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_data/clk-davinci-pll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_data/davinci-cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <mach/da8xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <mach/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <clocksource/timer-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DA850_PLL1_BASE 0x01e1a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DA850_TIMER64P2_BASE 0x01f0c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DA850_TIMER64P3_BASE 0x01f0d000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DA850_REF_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Device specific mux setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * soc description mux mode mode mux dbg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * reg offset mask mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct mux_config da850_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef CONFIG_DAVINCI_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* UART0 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* UART1 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* UART2 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* I2C1 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* I2C0 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* EMAC function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* McASP function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* LCD function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* MMC/SD0 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* MMC/SD1 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* EMIF2.5/EMIFA function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* GPIO function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* VPIF Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* VPIF Display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) const short da850_i2c0_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DA850_I2C0_SDA, DA850_I2C0_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const short da850_i2c1_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DA850_I2C1_SCL, DA850_I2C1_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const short da850_lcdcntl_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const short da850_vpif_capture_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DA850_VPIF_CLKIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const short da850_vpif_display_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DA850_VPIF_CLKO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct map_desc da850_io_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .virtual = IO_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .pfn = __phys_to_pfn(IO_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .length = IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .virtual = DA8XX_CP_INTC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .length = DA8XX_CP_INTC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Contents of JTAG ID register used to identify exact cpu type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct davinci_id da850_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .variant = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .part_no = 0xb7d1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .manufacturer = 0x017, /* 0x02f >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .cpu_id = DAVINCI_CPU_ID_DA850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .name = "da850/omap-l138",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .variant = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .part_no = 0xb7d1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .manufacturer = 0x017, /* 0x02f >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .cpu_id = DAVINCI_CPU_ID_DA850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "da850/omap-l138/am18x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Bottom half of timer 0 is used for clock_event, top half for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct davinci_timer_cfg da850_timer_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * According to the TRM, minimum PLLM results in maximum power savings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * The OPP definitions below should keep the PLLM as low as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * The output of the PLLM must be between 300 to 600 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct da850_opp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int freq; /* in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int cvdd_min; /* in uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int cvdd_max; /* in uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct da850_opp da850_opp_456 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .freq = 456000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .prediv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .mult = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .postdiv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .cvdd_min = 1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .cvdd_max = 1350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct da850_opp da850_opp_408 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .freq = 408000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .prediv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .mult = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .postdiv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .cvdd_min = 1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .cvdd_max = 1350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct da850_opp da850_opp_372 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .freq = 372000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .prediv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .mult = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .postdiv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .cvdd_min = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .cvdd_max = 1320000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct da850_opp da850_opp_300 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .freq = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .prediv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .mult = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .postdiv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .cvdd_min = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .cvdd_max = 1320000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct da850_opp da850_opp_200 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .freq = 200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .prediv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .mult = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .postdiv = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .cvdd_min = 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .cvdd_max = 1160000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct da850_opp da850_opp_96 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .freq = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .prediv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .mult = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .postdiv = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .cvdd_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .cvdd_max = 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define OPP(freq) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .driver_data = (unsigned int) &da850_opp_##freq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .frequency = freq * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct cpufreq_frequency_table da850_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) OPP(456),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) OPP(408),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) OPP(372),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) OPP(300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) OPP(200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) OPP(96),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .driver_data = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .frequency = CPUFREQ_TABLE_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int da850_set_voltage(unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int da850_regulator_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct davinci_cpufreq_config cpufreq_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .freq_table = da850_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .init = da850_regulator_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .set_voltage = da850_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct regulator *cvdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int da850_set_voltage(unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct da850_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!cvdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int da850_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cvdd = regulator_get(NULL, "cvdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) " voltage scaling unsupported\n")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return PTR_ERR(cvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct platform_device da850_cpufreq_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .name = "cpufreq-davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .platform_data = &cpufreq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned int da850_max_speed = 300000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int da850_register_cpufreq(char *async_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* cpufreq driver can help keep an "async" clock constant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (async_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk_add_alias("async", da850_cpufreq_device.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) async_clk, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (da850_freq_table[i].frequency <= da850_max_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cpufreq_info.freq_table = &da850_freq_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return platform_device_register(&da850_cpufreq_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int __init da850_register_cpufreq(char *async_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* VPIF resource, platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct resource da850_vpif_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .start = DA8XX_VPIF_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .end = DA8XX_VPIF_BASE + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct platform_device da850_vpif_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .name = "vpif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .dma_mask = &da850_vpif_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .resource = da850_vpif_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .num_resources = ARRAY_SIZE(da850_vpif_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct resource da850_vpif_display_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static struct platform_device da850_vpif_display_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .name = "vpif_display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .dma_mask = &da850_vpif_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .resource = da850_vpif_display_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static struct resource da850_vpif_capture_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct platform_device da850_vpif_capture_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .name = "vpif_capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .dma_mask = &da850_vpif_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .resource = da850_vpif_capture_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int __init da850_register_vpif(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return platform_device_register(&da850_vpif_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int __init da850_register_vpif_display(struct vpif_display_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *display_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) da850_vpif_display_dev.dev.platform_data = display_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return platform_device_register(&da850_vpif_display_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int __init da850_register_vpif_capture(struct vpif_capture_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *capture_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) da850_vpif_capture_dev.dev.platform_data = capture_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return platform_device_register(&da850_vpif_capture_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static struct davinci_gpio_platform_data da850_gpio_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .no_auto_base = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .ngpio = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int __init da850_register_gpio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return da8xx_register_gpio(&da850_gpio_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const struct davinci_soc_info davinci_soc_info_da850 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .io_desc = da850_io_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .io_desc_num = ARRAY_SIZE(da850_io_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .ids = da850_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ids_num = ARRAY_SIZE(da850_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .pinmux_pins = da850_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .pinmux_pins_num = ARRAY_SIZE(da850_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .emac_pdata = &da8xx_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .sram_dma = DA8XX_SHARED_RAM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .sram_len = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) void __init da850_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) davinci_common_init(&davinci_soc_info_da850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const struct davinci_cp_intc_config da850_cp_intc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .start = DA8XX_CP_INTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .num_irqs = DA850_N_CP_INTC_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) void __init da850_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) davinci_cp_intc_init(&da850_cp_intc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) void __init da850_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void __iomem *pll0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct regmap *cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cfgchip = da8xx_get_cfgchip();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) da850_pll0_init(NULL, pll0, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) clk = clk_get(NULL, "timer0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pr_err("Unable to get the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) rv = davinci_timer_register(clk, &da850_timer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) WARN(rv, "Unable to register the timer: %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct resource da850_pll1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .start = DA850_PLL1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .end = DA850_PLL1_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct davinci_pll_platform_data da850_pll1_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static struct platform_device da850_pll1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .name = "da850-pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .resource = da850_pll1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .num_resources = ARRAY_SIZE(da850_pll1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .platform_data = &da850_pll1_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct resource da850_psc0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .start = DA8XX_PSC0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .end = DA8XX_PSC0_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct platform_device da850_psc0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .name = "da850-psc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .resource = da850_psc0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .num_resources = ARRAY_SIZE(da850_psc0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static struct resource da850_psc1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .start = DA8XX_PSC1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .end = DA8XX_PSC1_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct platform_device da850_psc1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .name = "da850-psc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .resource = da850_psc1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .num_resources = ARRAY_SIZE(da850_psc1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static struct platform_device da850_async1_clksrc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .name = "da850-async1-clksrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .platform_data = &da850_async1_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct platform_device da850_async3_clksrc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .name = "da850-async3-clksrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .platform_data = &da850_async3_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static struct platform_device da850_tbclksync_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .name = "da830-tbclksync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .platform_data = &da850_tbclksync_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) void __init da850_register_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* PLL0 is registered in da850_init_time() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) platform_device_register(&da850_pll1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) platform_device_register(&da850_async1_clksrc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) platform_device_register(&da850_async3_clksrc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) platform_device_register(&da850_psc0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) platform_device_register(&da850_psc1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) platform_device_register(&da850_tbclksync_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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