^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DA830/OMAP L137 chip specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Mark A. Greer <mgreer@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2009 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqchip/irq-davinci-cp-intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <mach/da8xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <clocksource/timer-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Offsets of the 8 compare registers on the da830 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DA830_CMP12_0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DA830_CMP12_1 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DA830_CMP12_2 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DA830_CMP12_3 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DA830_CMP12_4 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DA830_CMP12_5 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DA830_CMP12_6 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DA830_CMP12_7 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DA830_REF_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Device specific mux setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * soc description mux mode mode mux dbg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * reg offset mask mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct mux_config da830_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #ifdef CONFIG_DAVINCI_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) const short da830_emif25_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const short da830_spi0_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DA830_NSPI0_SCS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) const short da830_spi1_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DA830_NSPI1_SCS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const short da830_mmc_sd_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DA830_MMCSD_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const short da830_uart0_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) const short da830_uart1_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DA830_UART1_RXD, DA830_UART1_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) const short da830_uart2_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DA830_UART2_RXD, DA830_UART2_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) const short da830_usb20_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) const short da830_usb11_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DA830_USB_REFCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) const short da830_uhpi_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) DA830_NUHPI_HINT, DA830_NUHPI_HRDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) const short da830_cpgmac_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DA830_MDIO_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) const short da830_emif3c_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) const short da830_mcasp0_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const short da830_mcasp1_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) const short da830_mcasp2_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) const short da830_i2c0_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DA830_I2C0_SDA, DA830_I2C0_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) const short da830_i2c1_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) DA830_I2C1_SCL, DA830_I2C1_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) const short da830_lcdcntl_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DA830_LCD_MCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) const short da830_pwm_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) const short da830_ecap0_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DA830_ECAP0_APWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) const short da830_ecap1_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) DA830_ECAP1_APWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const short da830_ecap2_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DA830_ECAP2_APWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) const short da830_eqep0_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) const short da830_eqep1_pins[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static struct map_desc da830_io_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .virtual = IO_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .pfn = __phys_to_pfn(IO_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .length = IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .virtual = DA8XX_CP_INTC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .length = DA8XX_CP_INTC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Contents of JTAG ID register used to identify exact cpu type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct davinci_id da830_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .variant = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .part_no = 0xb7df,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .manufacturer = 0x017, /* 0x02f >> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .cpu_id = DAVINCI_CPU_ID_DA830,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .name = "da830/omap-l137 rev1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .variant = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .part_no = 0xb7df,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .cpu_id = DAVINCI_CPU_ID_DA830,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .name = "da830/omap-l137 rev1.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .variant = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .part_no = 0xb7df,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .cpu_id = DAVINCI_CPU_ID_DA830,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .name = "da830/omap-l137 rev2.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static struct davinci_gpio_platform_data da830_gpio_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .no_auto_base = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .ngpio = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int __init da830_register_gpio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return da8xx_register_gpio(&da830_gpio_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Bottom half of timer0 is used both for clock even and clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * Top half is used by DSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct davinci_timer_cfg da830_timer_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .cmp_off = DA830_CMP12_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const struct davinci_soc_info davinci_soc_info_da830 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .io_desc = da830_io_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .io_desc_num = ARRAY_SIZE(da830_io_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .ids = da830_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .ids_num = ARRAY_SIZE(da830_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .pinmux_pins = da830_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .pinmux_pins_num = ARRAY_SIZE(da830_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .emac_pdata = &da8xx_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void __init da830_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) davinci_common_init(&davinci_soc_info_da830);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const struct davinci_cp_intc_config da830_cp_intc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .start = DA8XX_CP_INTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .num_irqs = DA830_N_CP_INTC_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) void __init da830_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) davinci_cp_intc_init(&da830_cp_intc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) void __init da830_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) void __iomem *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) pll = ioremap(DA8XX_PLL0_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) da830_pll_init(NULL, pll, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clk = clk_get(NULL, "timer0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pr_err("Unable to get the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) rv = davinci_timer_register(clk, &da830_timer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) WARN(rv, "Unable to register the timer: %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct resource da830_psc0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .start = DA8XX_PSC0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .end = DA8XX_PSC0_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct platform_device da830_psc0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .name = "da830-psc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .resource = da830_psc0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .num_resources = ARRAY_SIZE(da830_psc0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static struct resource da830_psc1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .start = DA8XX_PSC1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .end = DA8XX_PSC1_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static struct platform_device da830_psc1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .name = "da830-psc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .resource = da830_psc1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .num_resources = ARRAY_SIZE(da830_psc1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) void __init da830_register_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* PLL is registered in da830_init_time() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) platform_device_register(&da830_psc0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) platform_device_register(&da830_psc1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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