Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * TI DaVinci clock definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2006-2007 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2008-2009 Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ARCH_ARM_DAVINCI_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* PLL/Reset register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLLCTL          0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLLCTL_PLLEN    BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PLLCTL_PLLPWRDN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLLCTL_PLLRST	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLLCTL_PLLDIS	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLLCTL_PLLENSRC	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLLCTL_CLKMODE  BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLLM		0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLLM_PLLM_MASK  0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PREDIV          0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLLDIV1         0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLLDIV2         0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLLDIV3         0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define POSTDIV         0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BPDIV           0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLLCMD		0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLLSTAT		0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLLALNCTL	0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLLDCHANGE	0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLLCKEN		0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLLCKSTAT	0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLLSYSTAT	0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLLDIV4         0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLLDIV5         0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLLDIV6         0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLLDIV7         0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLLDIV8         0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLLDIV9         0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLLDIV_EN       BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLLDIV_RATIO_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * is ~25MHz. Units are micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLL_BYPASS_TIME		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLL_RESET_TIME		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  * Units are micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLL_LOCK_TIME		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif