^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Neuros Technologies OSD2 board support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Modified from original 644X-EVM board support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 2008 (c) Neuros Technology, LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The Neuros OSD 2.0 is the hardware component of the Neuros Open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Internet Television Platform. Hardware is very close to TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * DM644X-EVM board. It has:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Additionally realtime clock, IR remote control receiver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IR Blaster based on MSP430 (firmware although is different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * with PATA interface, two muxed red-green leds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * For more information please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/i2c-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/mmc-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_data/mtd-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_data/usb-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LXT971_PHY_ID 0x001378e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LXT971_PHY_MASK 0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NTOSD2_MSP430_I2C_ADDR 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NTOSD2_MSP430_IRQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 2048 blocks in the device, 64 pages per block, 2048 bytes per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NAND_BLOCK_SIZE SZ_128K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* UBL (a few copies) plus U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .size = 15 * NAND_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* U-Boot environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .name = "params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .size = 1 * NAND_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* File System */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .name = "filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* A few blocks at end hold a flash Bad Block Table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .core_chipsel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .parts = davinci_ntosd2_nandflash_partition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .ecc_bits = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .bbt_options = NAND_BBT_USE_FLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct resource davinci_ntosd2_nandflash_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct platform_device davinci_ntosd2_nandflash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "davinci_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .platform_data = &davinci_ntosd2_nandflash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .resource = davinci_ntosd2_nandflash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct platform_device davinci_fb_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "davincifb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .dma_mask = &davinci_fb_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .num_resources = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct gpio_led ntosd2_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .name = "led1_green", .gpio = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .name = "led1_red", .gpio = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .name = "led2_green", .gpio = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .name = "led2_red", .gpio = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct gpio_led_platform_data ntosd2_leds_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .num_leds = ARRAY_SIZE(ntosd2_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .leds = ntosd2_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct platform_device ntosd2_leds_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "leds-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .platform_data = &ntosd2_leds_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct platform_device *davinci_ntosd2_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) &davinci_fb_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &ntosd2_leds_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void __init davinci_ntosd2_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dm644x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .wires = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IS_ENABLED(CONFIG_PATA_BK3710))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static __init void davinci_ntosd2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct clk *aemif_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct davinci_soc_info *soc_info = &davinci_soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dm644x_register_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dm644x_init_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = dm644x_gpio_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) aemif_clk = clk_get(NULL, "aemif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk_prepare_enable(aemif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (HAS_ATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (HAS_NAND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "\tDisable IDE for NAND/NOR support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) davinci_init_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else if (HAS_NAND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) davinci_cfg_reg(DM644X_HPIEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) davinci_cfg_reg(DM644X_ATAEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* only one device will be jumpered and detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (HAS_NAND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) platform_device_register(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) &davinci_ntosd2_nandflash_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) platform_add_devices(davinci_ntosd2_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ARRAY_SIZE(davinci_ntosd2_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) davinci_serial_init(dm644x_serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dm644x_init_asp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) davinci_setup_usb(1000, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * The AEAWx are five new AEAW pins that can be muxed by separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * They are a bitmask for GPIO management. According TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * gpio(10,11,12,13) for leds any combination of bits works except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * four last. So we are to reset all five.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) davinci_cfg_reg(DM644X_AEAW0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) davinci_cfg_reg(DM644X_AEAW1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) davinci_cfg_reg(DM644X_AEAW2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) davinci_cfg_reg(DM644X_AEAW3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) davinci_cfg_reg(DM644X_AEAW4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .map_io = davinci_ntosd2_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .init_irq = dm644x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .init_time = dm644x_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .init_machine = davinci_ntosd2_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .init_late = davinci_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .dma_zone_size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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