^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Critical Link MityOMAP-L138 SoM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * version 2. This program is licensed "as is" without any warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) "MityOMAPL138: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spi/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <mach/da8xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_data/mtd-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_data/mtd-davinci-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/platform_data/ti-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/platform_data/spi-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MITYOMAPL138_PHY_ID ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FACTORY_CONFIG_MAGIC 0x012C0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FACTORY_CONFIG_VERSION 0x00010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Data Held in On-Board I2C device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct factory_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 fpga_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 serialnumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) char partnum[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct factory_config factory_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct part_no_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const char *part_no; /* part number string of interest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int max_freq; /* khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct part_no_info mityomapl138_pn_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .part_no = "L138-C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .max_freq = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .part_no = "L138-D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .max_freq = 375000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .part_no = "L138-F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .max_freq = 456000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .part_no = "1808-C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .max_freq = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .part_no = "1808-D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .max_freq = 375000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .part_no = "1808-F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .max_freq = 456000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .part_no = "1810-D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .max_freq = 375000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void mityomapl138_cpufreq_init(const char *partnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * the part number has additional characters beyond what is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * stored in the table. This information is not needed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * determining the speed grade, and would require several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * more table entries. Only check the first N characters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * for a match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) strlen(mityomapl138_pn_info[i].part_no))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) da850_max_speed = mityomapl138_pn_info[i].max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = da850_register_cpufreq("pll0_sysclk3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pr_warn("cpufreq registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void mityomapl138_cpufreq_init(const char *partnum) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int read_factory_config(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const char *partnum = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct nvmem_device *nvmem = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!IS_BUILTIN(CONFIG_NVMEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pr_warn("Factory Config not available without CONFIG_NVMEM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) goto bad_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &factory_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret != sizeof(struct factory_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_warn("Read Factory Config Failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) goto bad_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pr_warn("Factory Config Magic Wrong (%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) factory_config.magic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto bad_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (factory_config.version != FACTORY_CONFIG_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pr_warn("Factory Config Version Wrong (%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) factory_config.version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto bad_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) partnum = factory_config.partnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_info("Part Number = %s\n", partnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bad_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* default maximum speed is valid for all platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mityomapl138_cpufreq_init(partnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return NOTIFY_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct notifier_block mityomapl138_nvmem_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .notifier_call = read_factory_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * We don't define a cell for factory config as it will be accessed from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * board file using the nvmem notifier chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .offset = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .bytes = ETH_ALEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .cells = mityomapl138_nvmem_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .cell_name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .dev_id = "davinci_emac.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .con_id = "mac-address",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct property_entry mityomapl138_fd_chip_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PROPERTY_ENTRY_U32("pagesize", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PROPERTY_ENTRY_BOOL("read-only"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .bus_freq = 100, /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .bus_delay = 0, /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* TPS65023 voltage regulator support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* 1.2V Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .supply = "cvdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .supply = "usb0_vdda18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .supply = "usb1_vdda18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .supply = "ddr_dvdd18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .supply = "sata_vddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* 1.2V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .supply = "sata_vdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .supply = "usb_cvdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .supply = "pll0_vdda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .supply = "pll1_vdda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* 1.8V Aux LDO, not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .supply = "1.8v_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* FPGA VCC Aux (2.5 or 3.3) LDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .supply = "vccaux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct regulator_init_data tps65023_regulator_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* dcdc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .min_uV = 1150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .max_uV = 1350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .boot_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .consumer_supplies = tps65023_dcdc1_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* dcdc2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .min_uV = 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .max_uV = 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .valid_ops_mask = REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .boot_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .consumer_supplies = tps65023_dcdc2_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* dcdc3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .min_uV = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .max_uV = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .valid_ops_mask = REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .boot_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .consumer_supplies = tps65023_dcdc3_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* ldo1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .min_uV = 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .max_uV = 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .valid_ops_mask = REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .boot_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .consumer_supplies = tps65023_ldo1_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* ldo2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .min_uV = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .max_uV = 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .boot_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .consumer_supplies = tps65023_ldo2_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) I2C_BOARD_INFO("tps65023", 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .platform_data = &tps65023_regulator_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) I2C_BOARD_INFO("24c02", 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .properties = mityomapl138_fd_chip_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int __init pmic_tps65023_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return i2c_register_board_info(1, mityomap_tps65023_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ARRAY_SIZE(mityomap_tps65023_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * SPI Devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * SPI1_CS0: 8M Flash ST-M25P64-VME6G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct mtd_partition spi_flash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "ubl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .size = SZ_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .name = "u-boot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .size = SZ_512K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .name = "u-boot-env",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .size = SZ_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "periph-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .size = SZ_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .size = SZ_256K + SZ_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .size = SZ_2M + SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "fpga",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .size = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = "spare",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct flash_platform_data mityomapl138_spi_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "m25p80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .parts = spi_flash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .nr_parts = ARRAY_SIZE(spi_flash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .type = "m24p64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct davinci_spi_config spi_eprom_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .io_type = SPI_IO_TYPE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .c2tdelay = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .t2cdelay = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct spi_board_info mityomapl138_spi_flash_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .modalias = "m25p80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .platform_data = &mityomapl138_spi_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .controller_data = &spi_eprom_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .max_speed_hz = 30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .bus_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * MityDSP-L138 includes a 256 MByte large-page NAND flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * (128K blocks).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct mtd_partition mityomapl138_nandflash_partition[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .mask_flags = 0, /* MTD_WRITEABLE, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "homefs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static struct davinci_nand_pdata mityomapl138_nandflash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .core_chipsel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .parts = mityomapl138_nandflash_partition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .bbt_options = NAND_BBT_USE_FLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .options = NAND_BUSWIDTH_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct resource mityomapl138_nandflash_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .start = DA8XX_AEMIF_CS3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .start = DA8XX_AEMIF_CTL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct platform_device mityomapl138_aemif_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "davinci_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .platform_data = &mityomapl138_nandflash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .resource = mityomapl138_nandflash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct resource mityomapl138_aemif_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .start = DA8XX_AEMIF_CTL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .cs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct aemif_platform_data mityomapl138_aemif_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .abus_data = mityomapl138_aemif_abus_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .sub_devices = mityomapl138_aemif_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct platform_device mityomapl138_aemif_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .name = "ti-aemif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .platform_data = &mityomapl138_aemif_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .resource = mityomapl138_aemif_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void __init mityomapl138_setup_nand(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (platform_device_register(&mityomapl138_aemif_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pr_warn("%s: Cannot register AEMIF device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const short mityomap_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DA850_MDIO_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const short mityomap_rmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DA850_MDIO_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void __init mityomapl138_config_emac(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) void __iomem *cfg_chip3_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct davinci_soc_info *soc_info = &davinci_soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val = __raw_readl(cfg_chip3_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (soc_info->emac_pdata->rmii_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val |= BIT(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = davinci_cfg_reg_list(mityomap_rmii_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pr_info("RMII PHY configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) val &= ~BIT(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = davinci_cfg_reg_list(mityomap_mii_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pr_info("MII PHY configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pr_warn("mii/rmii mux setup failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* configure the CFGCHIP3 register for RMII or MII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) __raw_writel(val, cfg_chip3_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = da8xx_register_emac();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pr_warn("emac registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static void __init mityomapl138_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) da850_register_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* for now, no special EDMA channels are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = da850_register_edma(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pr_warn("edma registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = da8xx_register_watchdog();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pr_warn("watchdog registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) davinci_serial_init(da8xx_serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) nvmem_register_notifier(&mityomapl138_nvmem_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pr_warn("i2c0 registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = pmic_tps65023_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pr_warn("TPS65023 PMIC init failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mityomapl138_setup_nand();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = spi_register_board_info(mityomapl138_spi_flash_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ARRAY_SIZE(mityomapl138_spi_flash_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pr_warn("spi info registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = da8xx_register_spi_bus(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ARRAY_SIZE(mityomapl138_spi_flash_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pr_warn("spi 1 registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mityomapl138_config_emac();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = da8xx_register_rtc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pr_warn("rtc setup failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = da8xx_register_cpuidle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) pr_warn("cpuidle registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) davinci_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #ifdef CONFIG_SERIAL_8250_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int __init mityomapl138_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!machine_is_mityomapl138())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return add_preferred_console("ttyS", 1, "115200");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) console_initcall(mityomapl138_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void __init mityomapl138_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) da850_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .map_io = mityomapl138_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .init_irq = da850_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .init_time = da850_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .init_machine = mityomapl138_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .init_late = davinci_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .dma_zone_size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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