^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci DM646X EVM board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Derived from: arch/arm/mach-davinci/board-evm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) 2007-2008, MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Included Files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_data/pcf857x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/ti-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/i2c/tvp514x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/i2c/adv7343.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/platform_data/i2c-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/platform_data/mtd-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/platform_data/mtd-davinci-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NAND_BLOCK_SIZE SZ_128K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * and U-Boot environment this avoids dependency on any particular combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * of UBL, U-Boot or flashing tools etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct mtd_partition davinci_nand_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* UBL, U-Boot with environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .size = 16 * NAND_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .name = "filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .wsetup = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .wstrobe = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .whold = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .rsetup = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .rstrobe = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .rhold = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ta = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct davinci_nand_pdata davinci_nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .core_chipsel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .mask_cle = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mask_ale = 0x40000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .parts = davinci_nand_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .ecc_bits = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .options = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct resource davinci_nand_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct platform_device davinci_aemif_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "davinci_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .num_resources = ARRAY_SIZE(davinci_nand_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .resource = davinci_nand_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .platform_data = &davinci_nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct resource davinci_aemif_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct aemif_abus_data davinci_aemif_abus_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .cs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct aemif_platform_data davinci_aemif_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .abus_data = davinci_aemif_abus_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .num_abus_data = ARRAY_SIZE(davinci_aemif_abus_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .sub_devices = davinci_aemif_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct platform_device davinci_aemif_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "ti-aemif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .platform_data = &davinci_aemif_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .resource = davinci_aemif_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .num_resources = ARRAY_SIZE(davinci_aemif_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) IS_ENABLED(CONFIG_PATA_BK3710))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* CPLD Register 0 bits to control ATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DM646X_EVM_ATA_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DM646X_EVM_ATA_PWD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* CPLD Register 0 Client: used for I/O Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int cpld_reg0_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (HAS_ATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .buf = &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .buf = &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) i2c_transfer(client->adapter, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) i2c_transfer(client->adapter, msg + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct i2c_device_id cpld_reg_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { "cpld_reg0", 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct i2c_driver dm6467evm_cpld_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .driver.name = "cpld_reg0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .id_table = cpld_reg_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .probe_new = cpld_reg0_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* LEDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct gpio_led evm_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .name = "DS1", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .name = "DS2", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .name = "DS3", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .name = "DS4", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct gpio_led_platform_data evm_led_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .num_leds = ARRAY_SIZE(evm_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .leds = evm_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct platform_device *evm_led_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int evm_led_setup(struct i2c_client *client, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct gpio_led *leds = evm_leds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) while (ngpio--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) leds->gpio = gpio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) leds++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) evm_led_dev = platform_device_alloc("leds-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) platform_device_add_data(evm_led_dev, &evm_led_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sizeof(evm_led_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) evm_led_dev->dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) status = platform_device_add(evm_led_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) platform_device_put(evm_led_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) evm_led_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int evm_led_teardown(struct i2c_client *client, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (evm_led_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) platform_device_unregister(evm_led_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) evm_led_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int evm_sw_setup(struct i2c_client *client, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) char label[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) for (i = 0; i < 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) snprintf(label, 10, "user_sw%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) status = gpio_request(gpio, label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) evm_sw_gpio[i] = gpio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) status = gpio_direction_input(evm_sw_gpio[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) status = gpio_export(evm_sw_gpio[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) for (i = 0; i < 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (evm_sw_gpio[i] != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) gpio_free(evm_sw_gpio[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) evm_sw_gpio[i] = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int evm_sw_teardown(struct i2c_client *client, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 0; i < 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (evm_sw_gpio[i] != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) gpio_unexport(evm_sw_gpio[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) gpio_free(evm_sw_gpio[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) evm_sw_gpio[i] = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int evm_pcf_setup(struct i2c_client *client, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ngpio < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) status = evm_sw_setup(client, gpio, 4, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return evm_led_setup(client, gpio+4, 4, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int evm_pcf_teardown(struct i2c_client *client, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) BUG_ON(ngpio < 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) evm_sw_teardown(client, gpio, 4, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) evm_led_teardown(client, gpio+4, 4, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct pcf857x_platform_data pcf_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .gpio_base = DAVINCI_N_GPIO+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .setup = evm_pcf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .teardown = evm_pcf_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Most of this EEPROM is unused, but U-Boot uses some data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * - 0x7f00, 6 bytes Ethernet Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * - ... newer boards may have more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct nvmem_cell_info dm646x_evm_nvmem_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .offset = 0x7f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .bytes = ETH_ALEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct nvmem_cell_table dm646x_evm_nvmem_cell_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .cells = dm646x_evm_nvmem_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .ncells = ARRAY_SIZE(dm646x_evm_nvmem_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct nvmem_cell_lookup dm646x_evm_nvmem_cell_lookup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .cell_name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .dev_id = "davinci_emac.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .con_id = "mac-address",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct property_entry eeprom_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PROPERTY_ENTRY_U32("pagesize", 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static u8 dm646x_iis_serializer_direction[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static u8 dm646x_dit_serializer_direction[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) TX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct snd_platform_data dm646x_evm_snd_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .tx_dma_offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .rx_dma_offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .op_mode = DAVINCI_MCASP_IIS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .tdm_slots = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .serial_dir = dm646x_iis_serializer_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .asp_chan_q = EVENTQ_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .tx_dma_offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .rx_dma_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .op_mode = DAVINCI_MCASP_DIT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .tdm_slots = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .serial_dir = dm646x_dit_serializer_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .asp_chan_q = EVENTQ_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #ifdef CONFIG_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct i2c_client *cpld_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int cpld_video_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cpld_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int cpld_video_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cpld_client = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct i2c_device_id cpld_video_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { "cpld_video", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct i2c_driver cpld_video_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "cpld_video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .probe_new = cpld_video_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .remove = cpld_video_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .id_table = cpld_video_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void evm_init_cpld(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) i2c_add_driver(&cpld_video_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct i2c_board_info __initdata i2c_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) I2C_BOARD_INFO("24c256", 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .properties = eeprom_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) I2C_BOARD_INFO("pcf8574a", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .platform_data = &pcf_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) I2C_BOARD_INFO("cpld_reg0", 0x3a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) I2C_BOARD_INFO("tlv320aic33", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) I2C_BOARD_INFO("cpld_video", 0x3b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct davinci_i2c_platform_data i2c_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .bus_freq = 100 /* kHz */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .bus_delay = 0 /* usec */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define VCH2CLK_SYSCLK8 (BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define VCH3CLK_SYSCLK8 (BIT(13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define VIDCH2CLK (BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define VIDCH3CLK (BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define VIDCH1CLK (BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define TVP7002_INPUT (BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define TVP5147_INPUT (~BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define VPIF_INPUT_ONE_CHANNEL (BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define TVP5147_CH0 "tvp514x-0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define TVP5147_CH1 "tvp514x-1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* spin lock for updating above registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static spinlock_t vpif_reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int set_vpif_clock(int mux_mode, int hd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!cpld_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* disable the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) spin_lock_irqsave(&vpif_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) value |= (VIDCH3CLK | VIDCH2CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) spin_unlock_irqrestore(&vpif_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val = i2c_smbus_read_byte(cpld_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (mux_mode == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) val &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err = i2c_smbus_write_byte(cpld_client, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) value &= ~(VCH2CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) value &= ~(VCH3CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (hd >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) spin_lock_irqsave(&vpif_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* enable the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) value &= ~(VIDCH3CLK | VIDCH2CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spin_unlock_irqrestore(&vpif_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct vpif_subdev_info dm646x_vpif_subdev[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .name = "adv7343",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) I2C_BOARD_INFO("adv7343", 0x2a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .name = "ths7303",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) I2C_BOARD_INFO("ths7303", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct vpif_output dm6467_ch0_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .capabilities = V4L2_OUT_CAP_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .std = V4L2_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .subdev_name = "adv7343",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .output_route = ADV7343_COMPOSITE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "Component",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .subdev_name = "adv7343",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .output_route = ADV7343_COMPONENT_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .index = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = "S-Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .capabilities = V4L2_OUT_CAP_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .std = V4L2_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .subdev_name = "adv7343",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .output_route = ADV7343_SVIDEO_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct vpif_display_config dm646x_vpif_display_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .set_clock = set_vpif_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .subdevinfo = dm646x_vpif_subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .chan_config[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .outputs = dm6467_ch0_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .output_count = ARRAY_SIZE(dm6467_ch0_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .card_name = "DM646x EVM Video Display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * setup_vpif_input_path()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * @channel: channel id (0 - CH0, 1 - CH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * @sub_dev_name: ptr sub device name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * This will set vpif input to capture data from tvp514x or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * tvp7002.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int setup_vpif_input_path(int channel, const char *sub_dev_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* for channel 1, we don't do anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (channel != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!cpld_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val = i2c_smbus_read_byte(cpld_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!strcmp(sub_dev_name, TVP5147_CH0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) !strcmp(sub_dev_name, TVP5147_CH1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) val &= TVP5147_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) val |= TVP7002_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) err = i2c_smbus_write_byte(cpld_client, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * setup_vpif_input_channel_mode()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int setup_vpif_input_channel_mode(int mux_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (!cpld_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) val = i2c_smbus_read_byte(cpld_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) spin_lock_irqsave(&vpif_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (mux_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val &= VPIF_INPUT_TWO_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) value |= VIDCH1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val |= VPIF_INPUT_ONE_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) value &= ~VIDCH1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spin_unlock_irqrestore(&vpif_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) err = i2c_smbus_write_byte(cpld_client, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static struct tvp514x_platform_data tvp5146_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .clk_polarity = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .hs_polarity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .vs_polarity = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static struct vpif_subdev_info vpif_capture_sdev_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = TVP5147_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) I2C_BOARD_INFO("tvp5146", 0x5d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .platform_data = &tvp5146_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .name = TVP5147_CH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) I2C_BOARD_INFO("tvp5146", 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .platform_data = &tvp5146_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static struct vpif_input dm6467_ch0_inputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .input = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .capabilities = V4L2_IN_CAP_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .subdev_name = TVP5147_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .input_route = INPUT_CVBS_VI2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct vpif_input dm6467_ch1_inputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .input = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "S-Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .capabilities = V4L2_IN_CAP_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .subdev_name = TVP5147_CH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .input_route = INPUT_SVIDEO_VI2C_VI1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static struct vpif_capture_config dm646x_vpif_capture_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .setup_input_path = setup_vpif_input_path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .setup_input_channel_mode = setup_vpif_input_channel_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .subdev_info = vpif_capture_sdev_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .chan_config[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .inputs = dm6467_ch0_inputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .vpif_if = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .if_type = VPIF_IF_BT656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .hd_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .vd_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .fid_pol = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .chan_config[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .inputs = dm6467_ch1_inputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .vpif_if = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .if_type = VPIF_IF_BT656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .hd_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .vd_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .fid_pol = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .card_name = "DM646x EVM Video Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static void __init evm_init_video(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) spin_lock_init(&vpif_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dm646x_setup_vpif(&dm646x_vpif_display_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) &dm646x_vpif_capture_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void __init evm_init_i2c(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) davinci_init_i2c(&i2c_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) i2c_add_driver(&dm6467evm_cpld_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) evm_init_cpld();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) evm_init_video();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define DM646X_REF_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define DM646X_AUX_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define DM6467T_EVM_REF_FREQ 33000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void __init davinci_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dm646x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static void __init dm646x_evm_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dm646x_init_time(DM646X_REF_FREQ, DM646X_AUX_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void __init dm6467t_evm_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dm646x_init_time(DM6467T_EVM_REF_FREQ, DM646X_AUX_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * The following EDMA channels/slots are not being used by drivers (for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * reserved for codecs on the DSP side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const s16 dm646x_dma_rsv_chans[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* (offset, number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) { 0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {13, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {24, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {30, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {54, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {-1, -1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const s16 dm646x_dma_rsv_slots[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* (offset, number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { 0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {13, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {24, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {30, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {54, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {128, 384},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {-1, -1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct edma_rsv_info dm646x_edma_rsv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .rsv_chans = dm646x_dma_rsv_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .rsv_slots = dm646x_dma_rsv_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static __init void evm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct davinci_soc_info *soc_info = &davinci_soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dm646x_register_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = dm646x_gpio_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #ifdef CONFIG_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) nvmem_add_cell_table(&dm646x_evm_nvmem_cell_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) nvmem_add_cell_lookups(&dm646x_evm_nvmem_cell_lookup, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) evm_init_i2c();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) davinci_serial_init(dm646x_serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (machine_is_davinci_dm6467tevm())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (platform_device_register(&davinci_aemif_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pr_warn("%s: Cannot register AEMIF device.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dm646x_init_edma(dm646x_edma_rsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (HAS_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) davinci_init_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .map_io = davinci_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .init_irq = dm646x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .init_time = dm646x_evm_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .init_machine = evm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .init_late = davinci_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .dma_zone_size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .map_io = davinci_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .init_irq = dm646x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .init_time = dm6467t_evm_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .init_machine = evm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .init_late = davinci_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .dma_zone_size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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