^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci EVM board support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/pcf857x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/i2c/tvp514x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/i2c-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/platform_data/mtd-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/platform_data/mmc-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/platform_data/usb-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/platform_data/mtd-davinci-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/platform_data/ti-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LXT971_PHY_ID (0x001378e2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LXT971_PHY_MASK (0xfffffff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct mtd_partition davinci_evm_norflash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .size = 5 * SZ_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* bootloader params in the next 1 sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .size = SZ_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .size = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .mask_flags = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* file system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .mask_flags = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct physmap_flash_data davinci_evm_norflash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .parts = davinci_evm_norflash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * limits addresses to 16M, so using addresses past 16M will wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct resource davinci_evm_norflash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct platform_device davinci_evm_norflash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .platform_data = &davinci_evm_norflash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .resource = &davinci_evm_norflash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * It may used instead of the (default) NOR chip to boot, using TI's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * tools to install the secondary boot loader (UBL) and U-Boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct mtd_partition davinci_evm_nandflash_partition[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Bootloader layout depends on whose u-boot is installed, but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * can hide all the details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * - block 0 for u-boot environment ... in mainline u-boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * - blocks 6...? for u-boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * - blocks 16..23 for u-boot environment ... in TI's u-boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .size = SZ_256K + SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* File system (older GIT kernels started this on the 5MB mark) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* A few blocks at end hold a flash BBT ... created by TI's CCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * using flashwriter_nand.out, but ignored by TI's versions of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Linux and u-boot. We boot faster by using them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .wsetup = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .wstrobe = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .whold = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .rsetup = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .rstrobe = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .rhold = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .ta = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct davinci_nand_pdata davinci_evm_nandflash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .core_chipsel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .parts = davinci_evm_nandflash_partition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ecc_bits = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .bbt_options = NAND_BBT_USE_FLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .timing = &davinci_evm_nandflash_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct resource davinci_evm_nandflash_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct resource davinci_evm_aemif_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct aemif_abus_data davinci_evm_aemif_abus_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .cs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct platform_device davinci_evm_nandflash_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "davinci_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .platform_data = &davinci_evm_nandflash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .resource = davinci_evm_nandflash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct aemif_platform_data davinci_evm_aemif_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .abus_data = davinci_evm_aemif_abus_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .sub_devices = davinci_evm_nandflash_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct platform_device davinci_evm_aemif_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "ti-aemif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .platform_data = &davinci_evm_aemif_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .resource = davinci_evm_aemif_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct platform_device davinci_fb_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "davincifb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .dma_mask = &davinci_fb_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .num_resources = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .clk_polarity = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .hs_polarity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .vs_polarity = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Inputs available at the TVP5146 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "S-Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * this is the route info for connecting each input to decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * ouput that goes to vpfe. There is a one to one correspondence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * with tvp5146_inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct vpfe_route dm644xevm_tvp5146_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .input = INPUT_CVBS_VI2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .input = INPUT_SVIDEO_VI2C_VI1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = "tvp5146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .grp_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .inputs = dm644xevm_tvp5146_inputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .routes = dm644xevm_tvp5146_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .can_route = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .ccdc_if_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .if_type = VPFE_BT656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .hdpol = VPFE_PINPOL_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .vdpol = VPFE_PINPOL_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) I2C_BOARD_INFO("tvp5146", 0x5d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .platform_data = &dm644xevm_tvp5146_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct vpfe_config dm644xevm_capture_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .sub_devs = dm644xevm_vpfe_sub_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .card_name = "DM6446 EVM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .ccdc = "DM6446 CCDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct platform_device rtc_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "rtc_davinci_evm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * I2C GPIO expanders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* U2 -- LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct gpio_led evm_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .name = "DS8", .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .default_trigger = "heartbeat", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .name = "DS7", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .name = "DS6", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .name = "DS5", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { .name = "DS4", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { .name = "DS3", .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { .name = "DS2", .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .default_trigger = "mmc0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { .name = "DS1", .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .default_trigger = "disk-activity", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct gpio_led_platform_data evm_led_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .num_leds = ARRAY_SIZE(evm_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .leds = evm_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct platform_device *evm_led_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct gpio_led *leds = evm_leds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) while (ngpio--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) leds->gpio = gpio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) leds++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* what an extremely annoying way to be forced to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * device unregistration ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) evm_led_dev = platform_device_alloc("leds-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) platform_device_add_data(evm_led_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) &evm_led_data, sizeof evm_led_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) evm_led_dev->dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) status = platform_device_add(evm_led_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) platform_device_put(evm_led_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) evm_led_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (evm_led_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) platform_device_unregister(evm_led_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) evm_led_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct pcf857x_platform_data pcf_data_u2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .gpio_base = PCF_Uxx_BASE(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .setup = evm_led_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .teardown = evm_led_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* U18 - A/V clock generator and user switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int sw_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sw_show(struct device *d, struct device_attribute *a, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) strcpy(buf, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return strlen(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* export dip switch option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sw_gpio = gpio + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) status = gpio_request(sw_gpio, "user_sw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) status = gpio_direction_input(sw_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) status = device_create_file(&client->dev, &dev_attr_user_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gpio_free(sw_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) sw_gpio = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gpio_request(gpio + 3, "pll_fs2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) gpio_direction_output(gpio + 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) gpio_request(gpio + 2, "pll_fs1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) gpio_direction_output(gpio + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) gpio_request(gpio + 1, "pll_sr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) gpio_direction_output(gpio + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gpio_free(gpio + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) gpio_free(gpio + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) gpio_free(gpio + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (sw_gpio > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) device_remove_file(&client->dev, &dev_attr_user_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gpio_free(sw_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct pcf857x_platform_data pcf_data_u18 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .gpio_base = PCF_Uxx_BASE(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .setup = evm_u18_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .teardown = evm_u18_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* p0 = nDRV_VBUS (initial: don't supply it) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) gpio_request(gpio + 0, "nDRV_VBUS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) gpio_direction_output(gpio + 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* p1 = VDDIMX_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) gpio_request(gpio + 1, "VDDIMX_EN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) gpio_direction_output(gpio + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* p2 = VLYNQ_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) gpio_request(gpio + 2, "VLYNQ_EN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) gpio_direction_output(gpio + 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* p3 = n3V3_CF_RESET (initial: stay in reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) gpio_request(gpio + 3, "nCF_RESET");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) gpio_direction_output(gpio + 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* (p4 unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) gpio_request(gpio + 5, "WLAN_RESET");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) gpio_direction_output(gpio + 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* p6 = nATA_SEL (initial: select) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) gpio_request(gpio + 6, "nATA_SEL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) gpio_direction_output(gpio + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* p7 = nCF_SEL (initial: deselect) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) gpio_request(gpio + 7, "nCF_SEL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) gpio_direction_output(gpio + 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) gpio_free(gpio + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) gpio_free(gpio + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) gpio_free(gpio + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) gpio_free(gpio + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) gpio_free(gpio + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) gpio_free(gpio + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) gpio_free(gpio + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct pcf857x_platform_data pcf_data_u35 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .gpio_base = PCF_Uxx_BASE(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .setup = evm_u35_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .teardown = evm_u35_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Most of this EEPROM is unused, but U-Boot uses some data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * - 0x7f00, 6 bytes Ethernet Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * - ... newer boards may have more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .offset = 0x7f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .bytes = ETH_ALEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .cells = dm644evm_nvmem_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .cell_name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .dev_id = "davinci_emac.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .con_id = "mac-address",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct property_entry eeprom_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PROPERTY_ENTRY_U32("pagesize", 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * MSP430 supports RTC, card detection, input from IR remote, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * a bit more. It triggers interrupts on GPIO(7) from pressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * buttons on the IR remote, and for card detect switches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static struct i2c_client *dm6446evm_msp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int dm6446evm_msp_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dm6446evm_msp = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int dm6446evm_msp_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dm6446evm_msp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct i2c_device_id dm6446evm_msp_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { "dm6446evm_msp", 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { /* end of list */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static struct i2c_driver dm6446evm_msp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .driver.name = "dm6446evm_msp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .id_table = dm6446evm_msp_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .probe_new = dm6446evm_msp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .remove = dm6446evm_msp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int dm6444evm_msp430_get_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const char txbuf[2] = { 2, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .buf = (void __force *)txbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!dm6446evm_msp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msg[0].addr = dm6446evm_msp->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) msg[1].addr = dm6446evm_msp->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Command 4 == get input state, returns port 2 and port3 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * S Addr W [A] len=2 [A] cmd=4 [A]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return (buf[3] << 8) | buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int dm6444evm_mmc_get_cd(int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int status = dm6444evm_msp430_get_pins();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return (status < 0) ? status : !(status & BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int dm6444evm_mmc_get_ro(int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int status = dm6444evm_msp430_get_pins();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return (status < 0) ? status : status & BIT(6 + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct davinci_mmc_config dm6446evm_mmc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .get_cd = dm6444evm_mmc_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .get_ro = dm6444evm_mmc_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .wires = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct i2c_board_info __initdata i2c_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) I2C_BOARD_INFO("dm6446evm_msp", 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) I2C_BOARD_INFO("pcf8574", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .platform_data = &pcf_data_u2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) I2C_BOARD_INFO("pcf8574", 0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .platform_data = &pcf_data_u18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) I2C_BOARD_INFO("pcf8574", 0x3a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .platform_data = &pcf_data_u35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) I2C_BOARD_INFO("24c256", 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .properties = eeprom_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) I2C_BOARD_INFO("tlv320aic33", 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .dev_id = "i2c_davinci.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * which requires 100 usec of idle bus after i2c writes sent to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static struct davinci_i2c_platform_data i2c_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .bus_freq = 20 /* kHz */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .bus_delay = 100 /* usec */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .gpio_recovery = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void __init evm_init_i2c(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) davinci_init_i2c(&i2c_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) i2c_add_driver(&dm6446evm_msp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Fixed regulator support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) REGULATOR_SUPPLY("AVDD", "1-001b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) REGULATOR_SUPPLY("DRVDD", "1-001b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) REGULATOR_SUPPLY("IOVDD", "1-001b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) REGULATOR_SUPPLY("DVDD", "1-001b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* venc standard timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "ntsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .timings_type = VPBE_ENC_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .std_id = V4L2_STD_NTSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .interlaced = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .aspect = {11, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .fps = {30000, 1001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .left_margin = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .upper_margin = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .name = "pal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .timings_type = VPBE_ENC_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .std_id = V4L2_STD_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .interlaced = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .yres = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .aspect = {54, 59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .fps = {25, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .left_margin = 0x7e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .upper_margin = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* venc dv preset timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .name = "480p59_94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .timings_type = VPBE_ENC_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .interlaced = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .aspect = {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .fps = {5994, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .left_margin = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .upper_margin = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .name = "576p50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .timings_type = VPBE_ENC_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .dv_timings = V4L2_DV_BT_CEA_720X576P50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .interlaced = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .yres = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .aspect = {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .fps = {50, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .left_margin = 0x7e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .upper_margin = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * The outputs available from VPBE + encoders. Keep the order same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * as that of encoders. First those from venc followed by that from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * encoders. Index in the output refers to index on a particular encoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * Driver uses this index to pass it to encoder when it supports more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * than one output. Userspace applications use index of the array to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * set an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static struct vpbe_output dm644xevm_vpbe_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .std = VENC_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .capabilities = V4L2_OUT_CAP_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .default_mode = "ntsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .modes = dm644xevm_enc_std_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .name = "Component",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .default_mode = "480p59_94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .modes = dm644xevm_enc_preset_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static struct vpbe_config dm644xevm_display_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .module_name = "dm644x-vpbe-display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .osd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .venc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .outputs = dm644xevm_vpbe_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static struct platform_device *davinci_evm_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) &davinci_fb_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) &rtc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) davinci_evm_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dm644x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int davinci_phy_fixup(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* CRITICAL: Fix for increasing PHY signal drive strength for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * signal strength was low causing TX to fail randomly. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * fix is to Set bit 11 (Increased MII drive strength) of PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * register 26 (Digital Config register) on this phy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) control = phy_read(phydev, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) phy_write(phydev, 26, (control | 0x800));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) IS_ENABLED(CONFIG_PATA_BK3710))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define GPIO_nVBUS_DRV 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static struct gpiod_lookup_table dm644evm_usb_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .dev_id = "musb-davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GPIO_LOOKUP("davinci_gpio", GPIO_nVBUS_DRV, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static __init void davinci_evm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct clk *aemif_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct davinci_soc_info *soc_info = &davinci_soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dm644x_register_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dm644x_init_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = dm644x_gpio_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) aemif_clk = clk_get(NULL, "aemif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) clk_prepare_enable(aemif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (HAS_ATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (HAS_NAND || HAS_NOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "\tDisable IDE for NAND/NOR support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) davinci_init_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } else if (HAS_NAND || HAS_NOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) davinci_cfg_reg(DM644X_HPIEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) davinci_cfg_reg(DM644X_ATAEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* only one device will be jumpered and detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (HAS_NAND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) platform_device_register(&davinci_evm_aemif_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #ifdef CONFIG_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) evm_leds[7].default_trigger = "nand-disk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (HAS_NOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) } else if (HAS_NOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) platform_device_register(&davinci_evm_norflash_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) platform_add_devices(davinci_evm_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ARRAY_SIZE(davinci_evm_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #ifdef CONFIG_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) evm_init_i2c();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) davinci_setup_mmc(0, &dm6446evm_mmc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) davinci_serial_init(dm644x_serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dm644x_init_asp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* irlml6401 switches over 1A, in under 8 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) gpiod_add_lookup_table(&dm644evm_usb_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) davinci_setup_usb(1000, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (IS_BUILTIN(CONFIG_PHYLIB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* Register the fixup for PHY on DaVinci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) davinci_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Maintainer: MontaVista Software <source@mvista.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .map_io = davinci_evm_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .init_irq = dm644x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .init_time = dm644x_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .init_machine = davinci_evm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .init_late = davinci_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .dma_zone_size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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