^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci DM365 EVM board support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/spi/eeprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/ti-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/platform_data/i2c-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_data/mmc-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/mtd-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/platform_data/keyscan-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <media/i2c/ths7303.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <media/i2c/tvp514x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline int have_imager(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* REVISIT when it's supported, trigger via Kconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline int have_tvp7002(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* REVISIT when it's supported, trigger via Kconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * A MAX-II CPLD is used for various board control functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CPLD_TEST CPLD_OFFSET(0,1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CPLD_LEDS CPLD_OFFSET(0,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CPLD_MUX CPLD_OFFSET(0,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CPLD_POWER CPLD_OFFSET(1,1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CPLD_VIDEO CPLD_OFFSET(1,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CPLD_RESETS CPLD_OFFSET(4,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void __iomem *cpld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* NOTE: this is geared for the standard config, with a socketed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * swap chips with a different block size, partitioning will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * need to be changed. This NAND chip MT29F16G08FAA is the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * NAND shipped with the Spectrum Digital DM365 EVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NAND_BLOCK_SIZE SZ_128K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct mtd_partition davinci_nand_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* UBL (a few copies) plus U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .size = 30 * NAND_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* U-Boot environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .name = "params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .size = 2 * NAND_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "filesystem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .size = SZ_512M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = "filesystem2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* two blocks with bad block table (and mirror) at the end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct davinci_nand_pdata davinci_nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .core_chipsel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .mask_chipsel = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .parts = davinci_nand_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .bbt_options = NAND_BBT_USE_FLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .ecc_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct resource davinci_nand_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .start = DM365_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct platform_device davinci_aemif_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "davinci_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .num_resources = ARRAY_SIZE(davinci_nand_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .resource = davinci_nand_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .platform_data = &davinci_nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct resource davinci_aemif_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .start = DM365_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .cs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct aemif_platform_data davinci_aemif_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .abus_data = da850_evm_aemif_abus_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .sub_devices = davinci_aemif_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct platform_device davinci_aemif_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "ti-aemif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .platform_data = &davinci_aemif_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .resource = davinci_aemif_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .num_resources = ARRAY_SIZE(davinci_aemif_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct nvmem_cell_info davinci_nvmem_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .offset = 0x7f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .bytes = ETH_ALEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct nvmem_cell_table davinci_nvmem_cell_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cells = davinci_nvmem_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ncells = ARRAY_SIZE(davinci_nvmem_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .nvmem_name = "1-00500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .cell_name = "macaddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .dev_id = "davinci_emac.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .con_id = "mac-address",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct property_entry eeprom_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PROPERTY_ENTRY_U32("pagesize", 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct i2c_board_info i2c_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) I2C_BOARD_INFO("24c256", 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .properties = eeprom_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) I2C_BOARD_INFO("tlv320aic3x", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct davinci_i2c_platform_data i2c_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .bus_freq = 400 /* kHz */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .bus_delay = 0 /* usec */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Fixed regulator support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) REGULATOR_SUPPLY("AVDD", "1-0018"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) REGULATOR_SUPPLY("DRVDD", "1-0018"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) REGULATOR_SUPPLY("IOVDD", "1-0018"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) REGULATOR_SUPPLY("DVDD", "1-0018"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int dm365evm_keyscan_enable(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return davinci_cfg_reg(DM365_KEYSCAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static unsigned short dm365evm_keymap[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) KEY_KP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) KEY_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) KEY_EXIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) KEY_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) KEY_ENTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) KEY_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) KEY_KP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) KEY_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) KEY_MENU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) KEY_RECORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) KEY_REWIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) KEY_KPMINUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) KEY_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) KEY_FASTFORWARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) KEY_KPPLUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) KEY_PLAYPAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct davinci_ks_platform_data dm365evm_ks_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .device_enable = dm365evm_keyscan_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .keymap = dm365evm_keymap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .keymapsize = ARRAY_SIZE(dm365evm_keymap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .rep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Scan period = strobe + interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .strobe = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .interval = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int cpld_mmc_get_cd(int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!cpld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* low == card present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int cpld_mmc_get_ro(int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!cpld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* high == card's write protect switch active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct davinci_mmc_config dm365evm_mmc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .get_cd = cpld_mmc_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .get_ro = cpld_mmc_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .wires = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .max_freq = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void dm365evm_emac_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * EMAC pins are multiplexed with GPIO and UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Further details are available at the DM365 ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) davinci_cfg_reg(DM365_EMAC_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) davinci_cfg_reg(DM365_EMAC_TX_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) davinci_cfg_reg(DM365_EMAC_COL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) davinci_cfg_reg(DM365_EMAC_TXD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) davinci_cfg_reg(DM365_EMAC_TXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) davinci_cfg_reg(DM365_EMAC_TXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) davinci_cfg_reg(DM365_EMAC_TXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) davinci_cfg_reg(DM365_EMAC_RXD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) davinci_cfg_reg(DM365_EMAC_RXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) davinci_cfg_reg(DM365_EMAC_RXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) davinci_cfg_reg(DM365_EMAC_RXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) davinci_cfg_reg(DM365_EMAC_RX_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) davinci_cfg_reg(DM365_EMAC_RX_DV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) davinci_cfg_reg(DM365_EMAC_RX_ER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) davinci_cfg_reg(DM365_EMAC_CRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) davinci_cfg_reg(DM365_EMAC_MDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) davinci_cfg_reg(DM365_EMAC_MDCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * EMAC interrupts are multiplexed with GPIO interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Details are available at the DM365 ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void dm365evm_mmc_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * MMC/SD pins are multiplexed with GPIO and EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Further details are available at the DM365 ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) davinci_cfg_reg(DM365_SD1_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) davinci_cfg_reg(DM365_SD1_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) davinci_cfg_reg(DM365_SD1_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) davinci_cfg_reg(DM365_SD1_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) davinci_cfg_reg(DM365_SD1_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) davinci_cfg_reg(DM365_SD1_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct tvp514x_platform_data tvp5146_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .clk_polarity = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .hs_polarity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .vs_polarity = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Inputs available at the TVP5146 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct v4l2_input tvp5146_inputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "S-Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * this is the route info for connecting each input to decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * ouput that goes to vpfe. There is a one to one correspondence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * with tvp5146_inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static struct vpfe_route tvp5146_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .input = INPUT_CVBS_VI2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .input = INPUT_SVIDEO_VI2C_VI1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct vpfe_subdev_info vpfe_sub_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "tvp5146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .grp_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .num_inputs = ARRAY_SIZE(tvp5146_inputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .inputs = tvp5146_inputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .routes = tvp5146_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .can_route = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .ccdc_if_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .if_type = VPFE_BT656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .hdpol = VPFE_PINPOL_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .vdpol = VPFE_PINPOL_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) I2C_BOARD_INFO("tvp5146", 0x5d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .platform_data = &tvp5146_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct vpfe_config vpfe_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .sub_devs = vpfe_sub_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .card_name = "DM365 EVM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .ccdc = "ISIF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* venc standards timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "ntsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .timings_type = VPBE_ENC_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .std_id = V4L2_STD_NTSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .interlaced = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .aspect = {11, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .fps = {30000, 1001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .left_margin = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .upper_margin = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .name = "pal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .timings_type = VPBE_ENC_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .std_id = V4L2_STD_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .interlaced = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .yres = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .aspect = {54, 59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .fps = {25, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .left_margin = 0x7E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .upper_margin = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* venc dv timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .name = "480p59_94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .timings_type = VPBE_ENC_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .interlaced = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .aspect = {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .fps = {5994, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .left_margin = 0x8F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .upper_margin = 0x2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = "576p50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .timings_type = VPBE_ENC_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .dv_timings = V4L2_DV_BT_CEA_720X576P50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .interlaced = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .yres = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .aspect = {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .fps = {50, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .left_margin = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .upper_margin = 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .name = "720p60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .timings_type = VPBE_ENC_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .interlaced = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .yres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .aspect = {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .fps = {60, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .left_margin = 0x117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .right_margin = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .upper_margin = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .lower_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .hsync_len = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .vsync_len = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .name = "1080i60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .timings_type = VPBE_ENC_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .interlaced = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .xres = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .yres = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .aspect = {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .fps = {30, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .left_margin = 0xc9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .right_margin = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .upper_margin = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .lower_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .hsync_len = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .vsync_len = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * The outputs available from VPBE + ecnoders. Keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * the order same as that of encoders. First those from venc followed by that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * from encoders. Index in the output refers to index on a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * encoder.Driver uses this index to pass it to encoder when it supports more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * than one output. Application uses index of the array to set an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static struct vpbe_output dm365evm_vpbe_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .std = VENC_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .capabilities = V4L2_OUT_CAP_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .default_mode = "ntsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .modes = dm365evm_enc_std_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .if_params = MEDIA_BUS_FMT_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .name = "Component",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .default_mode = "480p59_94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .modes = dm365evm_enc_preset_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .if_params = MEDIA_BUS_FMT_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Amplifiers on the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static struct ths7303_platform_data ths7303_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .ch_1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .ch_2 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ch_3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static struct amp_config_info vpbe_amp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .module_name = "ths7303",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .is_i2c = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) I2C_BOARD_INFO("ths7303", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .platform_data = &ths7303_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static struct vpbe_config dm365evm_display_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .module_name = "dm365-vpbe-display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .amp = &vpbe_amp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .osd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .venc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .outputs = dm365evm_vpbe_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void __init evm_init_i2c(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) davinci_init_i2c(&i2c_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static inline int have_leds(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #ifdef CONFIG_LEDS_CLASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct cpld_led {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct led_classdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) const char *trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) } cpld_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { "dm365evm::ds2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { "dm365evm::ds3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { "dm365evm::ds4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { "dm365evm::ds5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { "dm365evm::ds6", "nand-disk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { "dm365evm::ds7", "mmc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { "dm365evm::ds8", "mmc0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { "dm365evm::ds9", "heartbeat", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u8 reg = __raw_readb(cpld + CPLD_LEDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (b != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) reg &= ~led->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) reg |= led->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __raw_writeb(reg, cpld + CPLD_LEDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static enum led_brightness cpld_led_get(struct led_classdev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u8 reg = __raw_readb(cpld + CPLD_LEDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return (reg & led->mask) ? LED_OFF : LED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int __init cpld_leds_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!have_leds() || !cpld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* setup LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) __raw_writeb(0xff, cpld + CPLD_LEDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct cpld_led *led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) led = kzalloc(sizeof(*led), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (!led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) led->cdev.name = cpld_leds[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) led->cdev.brightness_set = cpld_led_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) led->cdev.brightness_get = cpld_led_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) led->cdev.default_trigger = cpld_leds[i].trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) led->mask = BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (led_classdev_register(NULL, &led->cdev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) kfree(led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* run after subsys_initcall() for LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) fs_initcall(cpld_leds_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void __init evm_init_cpld(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u8 mux, resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct clk *aemif_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Make sure we can configure the CPLD through CS1. Then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * leave it on for later access to MMC and LED registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) aemif_clk = clk_get(NULL, "aemif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (IS_ERR(aemif_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) clk_prepare_enable(aemif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "cpld") == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!cpld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) SECTION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) pr_err("ERROR: can't map CPLD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) clk_disable_unprepare(aemif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* External muxing for some signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * NOTE: SW4 bus width setting must match!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* external keypad mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mux |= BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rc = platform_device_register(&davinci_aemif_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pr_warn("%s(): error registering the aemif device: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* no OneNAND support yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Leave external chips in reset when unused. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Static video input config with SN74CBT16214 1-of-3 mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * - port b1 == tvp7002 (mux lowbits == 1 or 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * - port b2 == imager (mux lowbits == 2 or 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * - port b3 == tvp5146 (mux lowbits == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * Runtime switching could work too, with limitations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (have_imager()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) label = "HD imager";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mux |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* externally mux MMC1/ENET/AIC33 to imager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mux |= BIT(6) | BIT(5) | BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct davinci_soc_info *soc_info = &davinci_soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* we can use MMC1 ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dm365evm_mmc_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) davinci_setup_mmc(1, &dm365evm_mmc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* ... and ENET ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dm365evm_emac_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) resets &= ~BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* ... and AIC33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) resets &= ~BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (have_tvp7002()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mux |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) resets &= ~BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) label = "tvp7002 HD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* default to tvp5146 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mux |= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) resets &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) label = "tvp5146 SD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __raw_writeb(mux, cpld + CPLD_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) __raw_writeb(resets, cpld + CPLD_RESETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pr_info("EVM: %s video input\n", label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void __init dm365_evm_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dm365_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static struct spi_eeprom at25640 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .byte_len = SZ_64K / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .name = "at25640",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .page_size = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .flags = EE_ADDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .modalias = "at25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .platform_data = &at25640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .max_speed_hz = 10 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static __init void dm365_evm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dm365_register_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = dm365_gpio_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) nvmem_add_cell_table(&davinci_nvmem_cell_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) evm_init_i2c();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) davinci_serial_init(dm365_serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dm365evm_emac_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dm365evm_mmc_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) davinci_setup_mmc(0, &dm365evm_mmc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* maybe setup mmc1/etc ... _after_ mmc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) evm_init_cpld();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dm365_init_asp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dm365_init_vc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dm365_init_rtc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dm365_init_ks(&dm365evm_ks_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dm365_init_spi0(BIT(0), dm365_evm_spi_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ARRAY_SIZE(dm365_evm_spi_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .map_io = dm365_evm_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .init_irq = dm365_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .init_time = dm365_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .init_machine = dm365_evm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .init_late = davinci_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .dma_zone_size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags