^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci EVM board support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Hilman, Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dm9000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/i2c/tvp514x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spi/eeprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_data/i2c-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_data/mtd-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_data/mmc-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/usb-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* NOTE: this is geared for the standard config, with a socketed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * swap chips, maybe with a different block size, partitioning may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * need to be changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NAND_BLOCK_SIZE SZ_128K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct mtd_partition davinci_nand_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* UBL (a few copies) plus U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .size = 15 * NAND_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* U-Boot environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = "params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .size = 1 * NAND_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = "filesystem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .size = SZ_512M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "filesystem2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* two blocks with bad block table (and mirror) at the end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct davinci_nand_pdata davinci_nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .core_chipsel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .mask_chipsel = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .parts = davinci_nand_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .bbt_options = NAND_BBT_USE_FLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .ecc_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct resource davinci_nand_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .start = DM355_ASYNC_EMIF_CONTROL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct platform_device davinci_nand_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "davinci_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_resources = ARRAY_SIZE(davinci_nand_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .resource = davinci_nand_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .platform_data = &davinci_nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .dev_id = "i2c_davinci.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct davinci_i2c_platform_data i2c_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .bus_freq = 400 /* kHz */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .bus_delay = 0 /* usec */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .gpio_recovery = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int dm355evm_mmc_gpios = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void dm355evm_mmcsd_gpios(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gpio_request(gpio + 0, "mmc0_ro");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gpio_request(gpio + 1, "mmc0_cd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) gpio_request(gpio + 2, "mmc1_ro");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) gpio_request(gpio + 3, "mmc1_cd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* we "know" these are input-only so we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * need to call gpio_direction_input()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dm355evm_mmc_gpios = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct i2c_board_info dm355evm_i2c_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { I2C_BOARD_INFO("dm355evm_msp", 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .platform_data = dm355evm_mmcsd_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* { plus irq }, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { I2C_BOARD_INFO("tlv320aic33", 0x1b), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void __init evm_init_i2c(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) davinci_init_i2c(&i2c_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) gpio_request(5, "dm355evm_msp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) gpio_direction_input(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dm355evm_i2c_info[0].irq = gpio_to_irq(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) i2c_register_board_info(1, dm355evm_i2c_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ARRAY_SIZE(dm355evm_i2c_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct resource dm355evm_dm9000_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .start = 0x04014000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .end = 0x04014001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .start = 0x04014002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .end = 0x04014003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct dm9000_plat_data dm335evm_dm9000_platdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct platform_device dm355evm_dm9000 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "dm9000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .resource = dm355evm_dm9000_rsrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .platform_data = &dm335evm_dm9000_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct tvp514x_platform_data tvp5146_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .clk_polarity = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .hs_polarity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .vs_polarity = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Inputs available at the TVP5146 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct v4l2_input tvp5146_inputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "S-Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .type = V4L2_INPUT_TYPE_CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .std = TVP514X_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * this is the route info for connecting each input to decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * ouput that goes to vpfe. There is a one to one correspondence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * with tvp5146_inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct vpfe_route tvp5146_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .input = INPUT_CVBS_VI2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .input = INPUT_SVIDEO_VI2C_VI1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct vpfe_subdev_info vpfe_sub_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "tvp5146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .grp_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .num_inputs = ARRAY_SIZE(tvp5146_inputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .inputs = tvp5146_inputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .routes = tvp5146_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .can_route = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .ccdc_if_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .if_type = VPFE_BT656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .hdpol = VPFE_PINPOL_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .vdpol = VPFE_PINPOL_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .board_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) I2C_BOARD_INFO("tvp5146", 0x5d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .platform_data = &tvp5146_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct vpfe_config vpfe_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .sub_devs = vpfe_sub_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .card_name = "DM355 EVM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .ccdc = "DM355 CCDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* venc standards timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = "ntsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .timings_type = VPBE_ENC_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .std_id = V4L2_STD_NTSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .interlaced = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .aspect = {11, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .fps = {30000, 1001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .left_margin = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .upper_margin = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .name = "pal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .timings_type = VPBE_ENC_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .std_id = V4L2_STD_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .interlaced = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .xres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .yres = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .aspect = {54, 59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .fps = {25, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .left_margin = 0x7E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .upper_margin = 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * The outputs available from VPBE + ecnoders. Keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * the order same as that of encoders. First those from venc followed by that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * from encoders. Index in the output refers to index on a particular encoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Driver uses this index to pass it to encoder when it supports more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * one output. Application uses index of the array to set an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct vpbe_output dm355evm_vpbe_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .output = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .type = V4L2_OUTPUT_TYPE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .std = VENC_STD_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .capabilities = V4L2_OUT_CAP_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .subdev_name = DM355_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .default_mode = "ntsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_modes = ARRAY_SIZE(dm355evm_enc_preset_timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .modes = dm355evm_enc_preset_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .if_params = MEDIA_BUS_FMT_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct vpbe_config dm355evm_display_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .module_name = "dm355-vpbe-display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .i2c_adapter_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .osd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .module_name = DM355_VPBE_OSD_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .venc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .module_name = DM355_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .num_outputs = ARRAY_SIZE(dm355evm_vpbe_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .outputs = dm355evm_vpbe_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct platform_device *davinci_evm_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &dm355evm_dm9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) &davinci_nand_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void __init dm355_evm_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dm355_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int dm355evm_mmc_get_cd(int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!gpio_is_valid(dm355evm_mmc_gpios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* low == card present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int dm355evm_mmc_get_ro(int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!gpio_is_valid(dm355evm_mmc_gpios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* high == card's write protect switch active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct davinci_mmc_config dm355evm_mmc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .get_cd = dm355evm_mmc_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .get_ro = dm355evm_mmc_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .wires = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .max_freq = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Don't connect anything to J10 unless you're only using USB host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * mode *and* have to do so with some kind of gender-bender. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * the ID pin won't need any help.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define USB_ID_VALUE 1 /* ID pulled low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct spi_eeprom at25640a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .byte_len = SZ_64K / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .name = "at25640a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .page_size = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .flags = EE_ADDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct spi_board_info dm355_evm_spi_info[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .modalias = "at25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .platform_data = &at25640a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static __init void dm355_evm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct clk *aemif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dm355_register_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = dm355_gpio_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gpio_request(1, "dm9000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) gpio_direction_input(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) clk_prepare_enable(aemif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) platform_add_devices(davinci_evm_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ARRAY_SIZE(davinci_evm_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) evm_init_i2c();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) davinci_serial_init(dm355_serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* NOTE: NAND flash timings set by the UBL are slower than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * but could be 0x0400008c for about 25% faster page reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) gpio_request(2, "usb_id_toggle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) gpio_direction_output(2, USB_ID_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* irlml6401 switches over 1A in under 8 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) davinci_setup_usb(1000, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) davinci_setup_mmc(0, &dm355evm_mmc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) davinci_setup_mmc(1, &dm355evm_mmc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dm355_init_spi0(BIT(0), dm355_evm_spi_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ARRAY_SIZE(dm355_evm_spi_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .map_io = dm355_evm_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .init_irq = dm355_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .init_time = dm355_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .init_machine = dm355_evm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .init_late = davinci_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .dma_zone_size = SZ_128M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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