Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * TI DaVinci Audio definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __ASM_ARCH_DAVINCI_ASP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __ASM_ARCH_DAVINCI_ASP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /* Bases of dm644x and dm355 register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define DAVINCI_ASP0_BASE	0x01E02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DAVINCI_ASP1_BASE	0x01E04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Bases of dm365 register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DAVINCI_DM365_ASP0_BASE	0x01D02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Bases of dm646x register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Bases of da850/da830 McASP0  register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Bases of da830 McASP1 register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Bases of da830 McASP2 register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DAVINCI_DA830_MCASP2_REG_BASE	0x01D08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* EDMA channels of dm644x and dm355 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DAVINCI_DMA_ASP0_TX	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DAVINCI_DMA_ASP0_RX	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DAVINCI_DMA_ASP1_TX	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DAVINCI_DMA_ASP1_RX	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* EDMA channels of dm646x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* EDMA channels of da850/da830 McASP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* EDMA channels of da830 McASP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAVINCI_DA830_DMA_MCASP1_AREVT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DAVINCI_DA830_DMA_MCASP1_AXEVT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* EDMA channels of da830 McASP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DAVINCI_DA830_DMA_MCASP2_AREVT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DAVINCI_DA830_DMA_MCASP2_AXEVT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DAVINCI_ASP0_RX_INT	DAVINCI_INTC_IRQ(IRQ_MBRINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DAVINCI_ASP0_TX_INT	DAVINCI_INTC_IRQ(IRQ_MBXINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DAVINCI_ASP1_RX_INT	DAVINCI_INTC_IRQ(IRQ_MBRINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DAVINCI_ASP1_TX_INT	DAVINCI_INTC_IRQ(IRQ_MBXINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif /* __ASM_ARCH_DAVINCI_ASP_H */