^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "cns3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) void cns3xxx_pwr_clk_en(unsigned int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 reg = __raw_readl(PM_CLK_GATE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg |= (block & PM_CLK_GATE_REG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __raw_writel(reg, PM_CLK_GATE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void cns3xxx_pwr_clk_dis(unsigned int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 reg = __raw_readl(PM_CLK_GATE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) reg &= ~(block & PM_CLK_GATE_REG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __raw_writel(reg, PM_CLK_GATE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void cns3xxx_pwr_power_up(unsigned int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Wait for 300us for the PLL output clock locked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) EXPORT_SYMBOL(cns3xxx_pwr_power_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void cns3xxx_pwr_power_down(unsigned int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* write '1' to power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg |= (block & CNS3XXX_PWR_PLL_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) EXPORT_SYMBOL(cns3xxx_pwr_power_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void cns3xxx_pwr_soft_rst_force(unsigned int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 reg = __raw_readl(PM_SOFT_RST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * bit 0, 28, 29 => program low to reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * the other else program low and then high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (block & 0x30000001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) reg &= ~(block & PM_SOFT_RST_REG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg &= ~(block & PM_SOFT_RST_REG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __raw_writel(reg, PM_SOFT_RST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg |= (block & PM_SOFT_RST_REG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __raw_writel(reg, PM_SOFT_RST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void cns3xxx_pwr_soft_rst(unsigned int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static unsigned int soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (soft_reset & block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SPI/I2C/GPIO use the same block, reset once. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) soft_reset |= block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) cns3xxx_pwr_soft_rst_force(block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * To reset, we hit the on-board reset register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * in the system FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * cns3xxx_cpu_clock - return CPU/L2 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * aclk: cpu clock/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * hclk: cpu clock/4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * pclk: cpu clock/8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int cns3xxx_cpu_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 reg = __raw_readl(PM_CLK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int cpu_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int div_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXPORT_SYMBOL(cns3xxx_cpu_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) atomic_t usb_pwr_ref = ATOMIC_INIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EXPORT_SYMBOL(usb_pwr_ref);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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