^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI-E support for CNS3xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Richard Liu <richard.liu@caviumnetworks.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2010 MontaVista Software, LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Anton Vorontsov <avorontsov@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "cns3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct cns3xxx_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void __iomem *host_regs; /* PCI config registers for host bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *cfg0_regs; /* PCI Type 0 config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void __iomem *cfg1_regs; /* PCI Type 1 config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int irqs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct resource res_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct resource res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool linked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pci_sys_data *root = sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return root->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return sysdata_to_cnspci(dev->sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return sysdata_to_cnspci(bus->sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int busno = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* If there is no link, just show the CNS PCI bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!cnspci->linked && busno > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * we still want to access it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * We place the host bridge on bus 0, and the directly connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * device on bus 1, slot 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (busno == 0) { /* internal PCIe bus, host bridge device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (devfn == 0) /* device# and function# are ignored by hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) base = cnspci->host_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return NULL; /* no such device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } else if (busno == 1) { /* directly connected PCIe device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (slot == 0) /* device# is ignored by hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) base = cnspci->cfg0_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return NULL; /* no such device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } else /* remote PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return base + where + (devfn << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 mask = (0x1ull << (size * 8)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int shift = (where % 4) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = pci_generic_config_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (where & 0xffc) == PCI_CLASS_REVISION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * RC's class is 0xb, but Linux PCI driver needs 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * for a PCIe bridge. So we must fixup the class code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * to 0x604 here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct resource *res_io = &cnspci->res_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct resource *res_mem = &cnspci->res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BUG_ON(request_resource(&iomem_resource, res_io) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) request_resource(&iomem_resource, res_mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct pci_ops cns3xxx_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .map_bus = cns3xxx_pci_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .read = cns3xxx_pci_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .write = pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int irq = cnspci->irqs[!!dev->bus->number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PCI_FUNC(dev->devfn), slot, pin, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct cns3xxx_pcie cns3xxx_pcie[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .res_io = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "PCIe0 I/O space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .start = CNS3XXX_PCIE0_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .res_mem = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .name = "PCIe0 non-prefetchable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .start = CNS3XXX_PCIE0_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .port = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .res_io = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "PCIe1 I/O space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .start = CNS3XXX_PCIE1_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .res_mem = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "PCIe1 non-prefetchable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .start = CNS3XXX_PCIE1_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .port = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int port = cnspci->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reg = __raw_readl(MISC_PCIE_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Enable Application Request to 1, it will exit L1 automatically,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * but when chip back, it will use another clock, still can use 0x1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reg |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __raw_writel(reg, MISC_PCIE_CTRL(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_info("PCIe: Port[%d] Check data link layer...", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (reg & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pr_info("Link up.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cnspci->linked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else if (time_after(jiffies, time + 50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pr_info("Device not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void __iomem *base = cnspci->host_regs + (where & 0xffc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 mask = (0x1ull << (size * 8)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int shift = (where % 4) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) v = readl_relaxed(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) v &= ~(mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) v |= (val & mask) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel_relaxed(v, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) readl_relaxed(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 mem_base = cnspci->res_mem.start >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 mem_limit = cnspci->res_mem.end >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 io_base = cnspci->res_io.start >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 io_limit = cnspci->res_io.end >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!cnspci->linked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Set Device Max_Read_Request_Size to 128 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pcie_bus_config = PCIE_BUS_PEER2PEER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Disable PCIe0 Interrupt Mask INTA to INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (fsr & (1 << 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regs->ARM_pc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void __init cns3xxx_pcie_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct hw_pci hw_pci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .nr_controllers = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .ops = &cns3xxx_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .setup = cns3xxx_pci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .map_irq = cns3xxx_pcie_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .private_data = &private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pcibios_min_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pcibios_min_mem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "imprecise external abort");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) private_data = &cns3xxx_pcie[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pci_common_init(&hw_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pci_assign_unassigned_resources();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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