^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * CNS3xxx common devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Scott Shu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2010 MontaVista Software, LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Anton Vorontsov <avorontsov@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cns3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * AHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct resource cns3xxx_ahci_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .start = CNS3XXX_SATA2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .start = IRQ_CNS3XXX_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .end = IRQ_CNS3XXX_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct platform_device cns3xxx_ahci_pdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .name = "ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .resource = cns3xxx_ahci_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .dma_mask = &cns3xxx_ahci_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __init cns3xxx_ahci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tmp = __raw_readl(MISC_SATA_POWER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __raw_writel(tmp, MISC_SATA_POWER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Enable SATA PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Enable SATA Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* De-Asscer SATA Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) platform_device_register(&cns3xxx_ahci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * SDHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct resource cns3xxx_sdhci_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .start = CNS3XXX_SDIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .start = IRQ_CNS3XXX_SDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .end = IRQ_CNS3XXX_SDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct platform_device cns3xxx_sdhci_pdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "sdhci-cns3xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .resource = cns3xxx_sdhci_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __init cns3xxx_sdhci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 gpioa_pins = __raw_readl(gpioa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* MMC/SD pins share with GPIOA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) gpioa_pins |= 0x1fff0004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __raw_writel(gpioa_pins, gpioa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) platform_device_register(&cns3xxx_sdhci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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