^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __MACH_BOARD_CNS3XXXH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __MACH_BOARD_CNS3XXXH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CNS3XXX_FLASH_SIZE SZ_256M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SMC_MEMC_STATUS_OFFSET 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMC_MEMIF_CFG_OFFSET 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SMC_MEMC_CFG_SET_OFFSET 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMC_MEMC_CFG_CLR_OFFSET 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMC_DIRECT_CMD_OFFSET 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SMC_SET_CYCLES_OFFSET 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SMC_SET_OPMODE_OFFSET 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SMC_REFRESH_PERIOD_0_OFFSET 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SMC_REFRESH_PERIOD_1_OFFSET 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SMC_SRAM_CYCLES0_0_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SMC_NAND_CYCLES0_0_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SMC_OPMODE0_0_OFFSET 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SMC_SRAM_CYCLES0_1_OFFSET 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SMC_NAND_CYCLES0_1_OFFSET 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SMC_OPMODE0_1_OFFSET 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SMC_USER_STATUS_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SMC_USER_CONFIG_OFFSET 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SMC_ECC_STATUS_OFFSET 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SMC_ECC_MEMCFG_OFFSET 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SMC_ECC_ADDR0_OFFSET 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SMC_ECC_ADDR1_OFFSET 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SMC_ECC_VALUE0_OFFSET 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SMC_ECC_VALUE1_OFFSET 0x31C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SMC_ECC_VALUE2_OFFSET 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SMC_ECC_VALUE3_OFFSET 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SMC_PERIPH_ID_0_OFFSET 0xFE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SMC_PERIPH_ID_1_OFFSET 0xFE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SMC_PERIPH_ID_2_OFFSET 0xFE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SMC_PERIPH_ID_3_OFFSET 0xFEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SMC_PCELL_ID_0_OFFSET 0xFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SMC_PCELL_ID_1_OFFSET 0xFF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SMC_PCELL_ID_2_OFFSET 0xFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SMC_PCELL_ID_3_OFFSET 0xFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RTC_SEC_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RTC_MIN_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RTC_HOUR_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RTC_DAY_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RTC_SEC_ALM_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RTC_MIN_ALM_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RTC_HOUR_ALM_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RTC_REC_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RTC_CTRL_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RTC_INTR_STS_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CNS3XXX_PM_BASE_VIRT 0xFB001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PM_CLK_GATE_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PM_SOFT_RST_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PM_HS_CFG_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PM_CACTIVE_STA_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PM_PWR_STA_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PM_SYS_CLK_CTRL_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PM_PLL_HM_PD_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CNS3XXX_UART0_BASE_VIRT 0xFB002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TIMER1_COUNTER_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TIMER1_AUTO_RELOAD_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TIMER1_MATCH_V1_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TIMER1_MATCH_V2_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TIMER2_COUNTER_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TIMER2_AUTO_RELOAD_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TIMER2_MATCH_V1_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TIMER2_MATCH_V2_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TIMER1_2_CONTROL_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TIMER_FREERUN_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TIMER_FREERUN_CONTROL_OFFSET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CNS3XXX_SATA2_SIZE SZ_16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Testchip peripheral and fpga gic regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CNS3XXX_TC11MP_TWD_BASE 0x90000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Misc block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Power management and clock control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PM_CSR_REG PMU_MEM_MAP(0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* PM_CLK_GATE_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PM_CLK_GATE_REG_OFFSET_SDIO (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PM_CLK_GATE_REG_OFFSET_GPU (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PM_CLK_GATE_REG_OFFSET_CIM (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PM_CLK_GATE_REG_OFFSET_LCDC (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PM_CLK_GATE_REG_OFFSET_I2S (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PM_CLK_GATE_REG_OFFSET_RAID (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PM_CLK_GATE_REG_OFFSET_SATA (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define PM_CLK_GATE_REG_OFFSET_TIMER (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PM_CLK_GATE_REG_OFFSET_HCIE (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PM_CLK_GATE_REG_OFFSET_GPIO (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PM_CLK_GATE_REG_OFFSET_UART3 (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PM_CLK_GATE_REG_OFFSET_UART2 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PM_CLK_GATE_REG_OFFSET_UART1 (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PM_CLK_GATE_REG_OFFSET_RTC (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PM_CLK_GATE_REG_OFFSET_GDMA (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* PM_SOFT_RST_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define PM_SOFT_RST_REG_OFFST_CPU1 (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PM_SOFT_RST_REG_OFFST_CPU0 (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define PM_SOFT_RST_REG_OFFST_SDIO (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define PM_SOFT_RST_REG_OFFST_GPU (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PM_SOFT_RST_REG_OFFST_CIM (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PM_SOFT_RST_REG_OFFST_LCDC (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PM_SOFT_RST_REG_OFFST_I2S (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PM_SOFT_RST_REG_OFFST_RAID (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PM_SOFT_RST_REG_OFFST_SATA (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PM_SOFT_RST_REG_OFFST_TIMER (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define PM_SOFT_RST_REG_OFFST_HCIE (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PM_SOFT_RST_REG_OFFST_SWITCH (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PM_SOFT_RST_REG_OFFST_GPIO (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PM_SOFT_RST_REG_OFFST_UART3 (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PM_SOFT_RST_REG_OFFST_UART2 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PM_SOFT_RST_REG_OFFST_UART1 (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PM_SOFT_RST_REG_OFFST_RTC (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PM_SOFT_RST_REG_OFFST_GDMA (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PM_SOFT_RST_REG_OFFST_DMC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* PMHS_CFG_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define PM_HS_CFG_REG_OFFSET_SDIO (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define PM_HS_CFG_REG_OFFSET_GPU (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PM_HS_CFG_REG_OFFSET_CIM (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PM_HS_CFG_REG_OFFSET_LCDC (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PM_HS_CFG_REG_OFFSET_I2S (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PM_HS_CFG_REG_OFFSET_RAID (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PM_HS_CFG_REG_OFFSET_SATA (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PM_HS_CFG_REG_OFFSET_TIMER (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PM_HS_CFG_REG_OFFSET_HCIE (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PM_HS_CFG_REG_OFFSET_SWITCH (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PM_HS_CFG_REG_OFFSET_GPIO (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PM_HS_CFG_REG_OFFSET_UART3 (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PM_HS_CFG_REG_OFFSET_UART2 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PM_HS_CFG_REG_OFFSET_UART1 (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PM_HS_CFG_REG_OFFSET_RTC (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PM_HS_CFG_REG_OFFSET_GDMA (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PM_HS_CFG_REG_OFFSET_DMC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PM_HS_CFG_REG_MASK (0x03FFFFBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* PM_CACTIVE_STA_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* PM_PWR_STA_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* PM_CLK_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PM_CPU_CLK_DIV(DIV) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PM_PLL_CPU_SEL(CPU) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* PM_PLL_LCD_I2S_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* PM_PLL_HM_PD_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* PM_WDT_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* PM_CSR_REG - Clock Scaling Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define PM_CSR_REG_OFFSET_CSR_EN (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define PM_CSR_REG_OFFSET_CSR_NUM (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Software reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * CNS3XXX support several power saving mode as following,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define CNS3XXX_PWR_CPU_MODE_DFS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define CNS3XXX_PWR_CPU_MODE_IDLE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define CNS3XXX_PWR_CPU_MODE_HALT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define CNS3XXX_PWR_CPU_MODE_DOZE (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define CNS3XXX_PWR_CPU_MODE_SLEEP (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Change CPU frequency and divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define CNS3XXX_PWR_PLL_CPU_333MHZ (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CNS3XXX_PWR_PLL_CPU_366MHZ (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define CNS3XXX_PWR_PLL_CPU_400MHZ (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define CNS3XXX_PWR_PLL_CPU_433MHZ (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define CNS3XXX_PWR_PLL_CPU_466MHZ (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define CNS3XXX_PWR_PLL_CPU_500MHZ (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define CNS3XXX_PWR_PLL_CPU_533MHZ (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define CNS3XXX_PWR_PLL_CPU_566MHZ (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define CNS3XXX_PWR_PLL_CPU_600MHZ (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define CNS3XXX_PWR_PLL_CPU_633MHZ (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define CNS3XXX_PWR_PLL_CPU_666MHZ (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define CNS3XXX_PWR_PLL_CPU_700MHZ (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Change DDR2 frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) void cns3xxx_pwr_soft_rst(unsigned int block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void cns3xxx_pwr_clk_en(unsigned int block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int cns3xxx_cpu_clock(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * ARM11 MPCore interrupt sources (primary GIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define IRQ_TC11MP_GIC_START 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #endif /* __MACH_BOARD_CNS3XXX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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