^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cavium Networks CNS3420 Validation Board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2000 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Scott Shu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2010 MontaVista Software, LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Anton Vorontsov <avorontsov@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/usb/ehci_pdriver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/ohci_pdriver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "cns3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * NOR Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct mtd_partition cns3420_nor_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "uboot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .size = 0x004C0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = "filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .size = 0x7000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "filesystem2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .size = 0x0AE0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "ubootenv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct physmap_flash_data cns3420_nor_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .parts = cns3420_nor_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct resource cns3420_nor_res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .start = CNS3XXX_FLASH_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct platform_device cns3420_nor_pdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .resource = &cns3420_nor_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .platform_data = &cns3420_nor_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void __init cns3420_early_serial_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef CONFIG_SERIAL_8250_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct uart_port cns3420_serial_port = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .mapbase = CNS3XXX_UART0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .irq = IRQ_CNS3XXX_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .uartclk = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .line = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .type = PORT_16550A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) early_serial_setup(&cns3420_serial_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct resource cns3xxx_usb_ehci_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .start = CNS3XXX_USB_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .end = CNS3XXX_USB_BASE + SZ_16M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .start = IRQ_CNS3XXX_USB_EHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int csn3xxx_usb_power_on(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * EHCI and OHCI share the same clock and power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * resetting twice would cause the 1st controller been reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Therefore only do power up at the first up device, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * power down at the last down device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Set USB AHB INCR length to 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (atomic_inc_return(&usb_pwr_ref) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MISC_CHIP_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void csn3xxx_usb_power_off(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * EHCI and OHCI share the same clock and power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * resetting twice would cause the 1st controller been reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Therefore only do power up at the first up device, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * power down at the last down device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (atomic_dec_return(&usb_pwr_ref) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .power_on = csn3xxx_usb_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .power_off = csn3xxx_usb_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct platform_device cns3xxx_usb_ehci_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "ehci-platform",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .resource = cns3xxx_usb_ehci_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .dma_mask = &cns3xxx_usb_ehci_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .platform_data = &cns3xxx_usb_ehci_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct resource cns3xxx_usb_ohci_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .start = CNS3XXX_USB_OHCI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .start = IRQ_CNS3XXX_USB_OHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .num_ports = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .power_on = csn3xxx_usb_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .power_off = csn3xxx_usb_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct platform_device cns3xxx_usb_ohci_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .name = "ohci-platform",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .resource = cns3xxx_usb_ohci_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .dma_mask = &cns3xxx_usb_ohci_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .platform_data = &cns3xxx_usb_ohci_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct platform_device *cns3420_pdevs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &cns3420_nor_pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) &cns3xxx_usb_ehci_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &cns3xxx_usb_ohci_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void __init cns3420_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cns3xxx_l2x0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cns3xxx_ahci_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) cns3xxx_sdhci_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pm_power_off = cns3xxx_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct map_desc cns3420_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .virtual = CNS3XXX_UART0_BASE_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .length = SZ_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void __init cns3420_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cns3xxx_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cns3420_early_serial_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .map_io = cns3420_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .init_irq = cns3xxx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .init_time = cns3xxx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .init_machine = cns3420_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .init_late = cns3xxx_pcie_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .restart = cns3xxx_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags