Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014-2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2014 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irqchip/irq-bcm2836.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "platsmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Size of mapped Cortex A9 SCU address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CORTEX_A9_SCU_SIZE	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SECONDARY_TIMEOUT_NS	NSEC_PER_MSEC	/* 1 msec (in nanoseconds) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define BOOT_ADDR_CPUID_MASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Name of device node property defining secondary boot register location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OF_SECONDARY_BOOT	"secondary-boot-reg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MPIDR_CPUID_BITMASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * Enable the Cortex A9 Snoop Control Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * By the time this is called we already know there are multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * cores present.  We assume we're running on a Cortex A9 processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * so any trouble getting the base address register or getting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * SCU base is a problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * Return 0 if successful or an error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int __init scu_a9_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned long config_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void __iomem *scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (!scu_a9_has_base()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		pr_err("no configuration base address register!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/* Config base address register value is zero for uniprocessor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	config_base = scu_a9_get_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (!config_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		pr_err("hardware reports only one core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (!scu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		pr_err("failed to remap config base (%lu/%u) for SCU\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			config_base, CORTEX_A9_SCU_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	scu_enable(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	iounmap(scu_base);	/* That's the last we'll need of this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static u32 secondary_boot_addr_for(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 secondary_boot_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)         if (!cpu_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		pr_err("Failed to find device tree node for CPU%u\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (of_property_read_u32(cpu_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				 OF_SECONDARY_BOOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				 &secondary_boot_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		pr_err("required secondary boot register not specified for CPU%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	of_node_put(cpu_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return secondary_boot_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int nsp_write_lut(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	void __iomem *sku_rom_lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	phys_addr_t secondary_startup_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (!secondary_boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	sku_rom_lut = ioremap((phys_addr_t)secondary_boot_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				      sizeof(phys_addr_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!sku_rom_lut) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	secondary_startup_phy = __pa_symbol(secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	writel_relaxed(secondary_startup_phy, sku_rom_lut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Ensure the write is visible to the secondary core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	iounmap(sku_rom_lut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* Enable the SCU on Cortex A9 based SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (scu_a9_enable()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/* Update the CPU present map to reflect uniprocessor mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		pr_warn("failed to enable A9 SCU - disabling SMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		init_cpu_present(&only_cpu_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * The ROM code has the secondary cores looping, waiting for an event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * When an event occurs each core examines the bottom two bits of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * secondary boot register.  When a core finds those bits contain its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * own core id, it performs initialization, including computing its boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * address by clearing the boot register value's bottom two bits.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * core signals that it is beginning its execution by writing its boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * address back to the secondary boot register, and finally jumps to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * that address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * So to start a core executing we need to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * - Encode the (hardware) CPU id with the bottom bits of the secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *   start address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * - Write that value into the secondary boot register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * - Generate an event to wake up the secondary CPU(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * - Wait for the secondary boot register to be re-written, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  *   indicates the secondary core has started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	void __iomem *boot_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	phys_addr_t boot_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u64 start_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32 boot_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	bool timeout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	cpu_id = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!secondary_boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	boot_reg = ioremap((phys_addr_t)secondary_boot_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				   sizeof(phys_addr_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!boot_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		pr_err("unable to map boot register for cpu %u\n", cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * Secondary cores will start in secondary_startup(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * defined in "arch/arm/kernel/head.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	boot_func = __pa_symbol(secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	BUG_ON(boot_func > (phys_addr_t)U32_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* The core to start is encoded in the low bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	boot_val = (u32)boot_func | cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	writel_relaxed(boot_val, boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	sev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* The low bits will be cleared once the core has started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	start_clock = local_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	while (!timeout && readl_relaxed(boot_reg) == boot_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	iounmap(boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	pr_err("timeout waiting for cpu %u to start\n", cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Cluster Dormant Control command to bring CPU into a running state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CDC_CMD			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CDC_CMD_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CDC_CMD_REG(cpu)	(CDC_CMD_OFFSET + 4*(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * BCM23550 has a Cluster Dormant Control block that keeps the core in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * idle state. A command needs to be sent to the block to bring the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * into running state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	void __iomem *cdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Make sure a CDC node exists before booting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * secondary core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	name = "brcm,bcm23550-cdc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	dn = of_find_compatible_node(NULL, NULL, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (!dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		pr_err("unable to find cdc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	cdc_base = of_iomap(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!cdc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		pr_err("unable to remap cdc base register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* Boot the secondary core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = kona_boot_secondary(cpu, idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/* Bring this CPU to RUN state so that nIRQ nFIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * signals are unblocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	iounmap(cdc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 * After wake up, secondary core branches to the startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * address programmed at SKU ROM LUT location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ret = nsp_write_lut(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		pr_err("unable to write startup addr to SKU ROM LUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/* Send a CPU wakeup interrupt to the secondary core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	void __iomem *intc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	name = "brcm,bcm2836-l1-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	dn = of_find_compatible_node(NULL, NULL, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (!dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		pr_err("unable to find intc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	intc_base = of_iomap(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!intc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		pr_err("unable to remap intc base register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	writel(virt_to_phys(secondary_startup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	       intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	dsb(sy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	sev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	iounmap(intc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct smp_operations kona_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.smp_boot_secondary	= kona_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			&kona_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct smp_operations bcm23550_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.smp_boot_secondary	= bcm23550_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			&bcm23550_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct smp_operations nsp_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.smp_boot_secondary	= nsp_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) const struct smp_operations bcm2836_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.smp_boot_secondary	= bcm2836_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops);