^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom STB CPU SMP and hotplug support for ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013-2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ZONE_MAN_CLKEN_MASK = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ZONE_MAN_RESET_CNTL_MASK = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ZONE_MAN_MEM_PWR_MASK = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ZONE_RESERVED_1_MASK = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ZONE_MAN_ISO_CNTL_MASK = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ZONE_MANUAL_CONTROL_MASK = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ZONE_PWR_DN_REQ_MASK = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ZONE_PWR_UP_REQ_MASK = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ZONE_BLK_RST_ASSERT_MASK = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ZONE_PWR_OFF_STATE_MASK = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ZONE_PWR_ON_STATE_MASK = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ZONE_DPG_PWR_STATE_MASK = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ZONE_MEM_PWR_STATE_MASK = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ZONE_RESET_STATE_MASK = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CPU0_PWR_ZONE_CTRL_REG = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CPU_RESET_CONFIG_REG = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void __iomem *cpubiuctrl_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void __iomem *hif_cont_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static u32 cpu0_pwr_zone_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u32 cpu_rst_cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static u32 hif_cont_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * one or more cache may be disabled, we must flush to ensure coherency. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * cannot use traditionl completion structures or spinlocks as they rely on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * coherency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int per_cpu_sw_state_rd(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return per_cpu(per_cpu_sw_state, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void per_cpu_sw_state_wr(u32 cpu, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) per_cpu(per_cpu_sw_state, cpu) = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void __iomem *pwr_ctrl_get_base(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) base += (cpu_logical_map(cpu) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static u32 pwr_ctrl_rd(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *base = pwr_ctrl_get_base(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return readl_relaxed(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void pwr_ctrl_set(unsigned int cpu, u32 val, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *base = pwr_ctrl_get_base(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel((readl(base) & mask) | val, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void pwr_ctrl_clr(unsigned int cpu, u32 val, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *base = pwr_ctrl_get_base(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel((readl(base) & mask) & ~val, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define POLL_TMOUT_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int pwr_ctrl_wait_tmout(unsigned int cpu, u32 set, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const unsigned long timeo = jiffies + msecs_to_jiffies(POLL_TMOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tmp = pwr_ctrl_rd(cpu) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!set == !tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } while (time_before(jiffies, timeo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tmp = pwr_ctrl_rd(cpu) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!set == !tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void cpu_rst_cfg_set(u32 cpu, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val |= BIT(cpu_logical_map(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val &= ~BIT(cpu_logical_map(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const int reg_ofs = cpu_logical_map(cpu) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void brcmstb_cpu_boot(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Mark this CPU as "up" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) per_cpu_sw_state_wr(cpu, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Set the reset vector to point to the secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cpu_set_boot_addr(cpu, __pa_symbol(secondary_startup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Unhalt the cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cpu_rst_cfg_set(cpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void brcmstb_cpu_power_on(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * The secondary cores power was cut, so we must go through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * power-on initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, 0xffffff00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pwr_ctrl_set(cpu, ZONE_RESERVED_1_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pwr_ctrl_set(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_MEM_PWR_STATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) panic("ZONE_MEM_PWR_STATE_MASK set timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pwr_ctrl_set(cpu, ZONE_MAN_CLKEN_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_DPG_PWR_STATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) panic("ZONE_DPG_PWR_STATE_MASK set timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pwr_ctrl_clr(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pwr_ctrl_set(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int brcmstb_cpu_get_power_state(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int tmp = pwr_ctrl_rd(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void brcmstb_cpu_die(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) v7_exit_coherency_flush(all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) per_cpu_sw_state_wr(cpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Sit and wait to die */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) wfi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* We should never get here... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int brcmstb_cpu_kill(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Ordinarily, the hardware forbids power-down of CPU0 (which is good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * because it is the boot CPU), but this is not true when using BPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * manual mode. Consequently, we must avoid turning off CPU0 here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * ensure that TI2C master reset will work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (cpu == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pr_warn("SMP: refusing to power off CPU0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) while (per_cpu_sw_state_rd(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pwr_ctrl_clr(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pwr_ctrl_clr(cpu, ZONE_MAN_CLKEN_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pwr_ctrl_clr(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_MEM_PWR_STATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) panic("ZONE_MEM_PWR_STATE_MASK clear timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pwr_ctrl_clr(cpu, ZONE_RESERVED_1_MASK, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_DPG_PWR_STATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) panic("ZONE_DPG_PWR_STATE_MASK clear timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Flush pipeline before resetting CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Assert reset on the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cpu_rst_cfg_set(cpu, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif /* CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct device_node *syscon_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) name = "syscon-cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) syscon_np = of_parse_phandle(np, name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!syscon_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_err("can't find phandle %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cpubiuctrl_block = of_iomap(syscon_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!cpubiuctrl_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pr_err("iomap failed for cpubiuctrl_block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) &cpu0_pwr_zone_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_err("failed to read 1st entry from %s property (%d)\n", name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) &cpu_rst_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pr_err("failed to read 2nd entry from %s property (%d)\n", name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) of_node_put(syscon_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int __init setup_hifcont_regs(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct device_node *syscon_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) name = "syscon-cont";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) syscon_np = of_parse_phandle(np, name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!syscon_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pr_err("can't find phandle %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hif_cont_block = of_iomap(syscon_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!hif_cont_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pr_err("iomap failed for hif_cont_block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Offset is at top of hif_cont_block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) hif_cont_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) of_node_put(syscon_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) name = "brcm,brcmstb-smpboot";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) np = of_find_compatible_node(NULL, NULL, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pr_err("can't find compatible node %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rc = setup_hifcpubiuctrl_regs(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) rc = setup_hifcont_regs(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) out_put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Missing the brcm,brcmstb-smpboot DT node? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!cpubiuctrl_block || !hif_cont_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Bring up power to the core if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (brcmstb_cpu_get_power_state(cpu) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) brcmstb_cpu_power_on(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) brcmstb_cpu_boot(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct smp_operations brcmstb_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .smp_boot_secondary = brcmstb_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .cpu_kill = brcmstb_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .cpu_die = brcmstb_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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