^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom BCM63138 PMB initialization for secondary CPU(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Florian Fainelli <f.fainelli@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/reset/bcm63xx_pmb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "bcm63xx_smp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* ARM Control register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CORE_PWR_CTRL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CORE_PWR_CTRL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_PWR_ON BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_LDO_PWR_ON BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_CLAMP_ON BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CPU_RESET_N(x) BIT(13 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NEON_RESET_N BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWR_CTRL_STATUS_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PWR_CTRL_STATUS_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWR_DOWN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWR_DOWN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* CPU Power control register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MEM_PWR_OK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MEM_PWR_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MEM_CLAMP_ON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MEM_PWR_OK_STATUS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MEM_PWR_ON_STATUS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MEM_PDA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MEM_PDA_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MEM_PDA_CPU_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MEM_PDA_NEON_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLAMP_ON BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PWR_OK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PWR_OK_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PWR_ON_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWR_CPU_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PWR_NEON_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PWR_ON_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PWR_OK_STATUS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PWR_OK_STATUS_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWR_ON_STATUS_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PWR_ON_STATUS_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ARM_CONTROL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ARM_PWR_CONTROL_BASE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ARM_PWR_CONTROL(x) (ARM_PWR_CONTROL_BASE + (x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ARM_NEON_L2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Perform a value write, then spin until the value shifted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * shift is seen, masked with mask and is different from cond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int bpcm_wr_rd_mask(void __iomem *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int addr, u32 off, u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 shift, u32 mask, u32 cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = bpcm_wr(master, addr, off, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = bpcm_rd(master, addr, off, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } while (((*val >> shift) & mask) != cond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Global lock to serialize accesses to the PMB registers while we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * are bringing up the secondary CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static DEFINE_SPINLOCK(pmb_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int bcm63xx_pmb_get_resources(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem **base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int *cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = of_property_read_u32(dn, "reg", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pr_err("CPU is missing a reg node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pr_err("CPU is missing a resets phandle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (args.args_count != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pr_err("reset-controller does not conform to reset-cells\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *base = of_iomap(args.np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!*base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pr_err("failed remapping PMB register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* We do not need the number of zones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *addr = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int bcm63xx_pmb_power_on_cpu(struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int cpu, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 val, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = bcm63xx_pmb_get_resources(dn, &base, &cpu, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* We would not know how to enable a third and greater CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) WARN_ON(cpu > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_lock_irqsave(&pmb_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Check if the CPU is already on and save the ARM_CONTROL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * value since we will use it later for CPU de-assert once done with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * the CPU-specific power sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ctrl & CPU_RESET_N(cpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pr_info("PMB: CPU%d is already powered on\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Power on PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = bpcm_rd(base, addr, ARM_PWR_CONTROL(cpu), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val |= (PWR_CPU_MASK << PWR_ON_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PWR_ON_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val |= (PWR_CPU_MASK << PWR_OK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PWR_OK_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val &= ~CLAMP_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Power on CPU<N> RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val &= ~(MEM_PDA_MASK << MEM_PDA_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= MEM_PWR_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0, MEM_PWR_ON_STATUS, MEM_PWR_ON_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val |= MEM_PWR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0, MEM_PWR_OK_STATUS, MEM_PWR_OK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) val &= ~MEM_CLAMP_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* De-assert CPU reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ctrl |= CPU_RESET_N(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = bpcm_wr(base, addr, ARM_CONTROL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_unlock_irqrestore(&pmb_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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