^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-at91/pm_slow_clock.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Savin Zlobec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * AT91SAM9 support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pm_data-offsets.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SRAMC_SELF_FRESH_ACTIVE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SRAMC_SELF_FRESH_EXIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) pmc .req r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) tmp1 .req r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) tmp2 .req r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) tmp3 .req r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Wait until master clock is ready (after switching master clock source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .macro wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 1: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) tst tmp1, #AT91_PMC_MCKRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) beq 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Wait until master oscillator has stabilized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .macro wait_moscrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 1: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) tst tmp1, #AT91_PMC_MOSCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) beq 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Wait for main oscillator selection is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .macro wait_moscsels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 1: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) tst tmp1, #AT91_PMC_MOSCSELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) beq 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Put the processor to enter the idle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .macro at91_cpu_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #if defined(CONFIG_CPU_V7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mov tmp1, #AT91_PMC_PCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) str tmp1, [pmc, #AT91_PMC_SCDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) wfi @ Wait For Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mcr p15, 0, tmp1, c7, c0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * void at91_suspend_sram_fn(struct at91_pm_data*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @input param:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @r0: base address of struct at91_pm_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ENTRY(at91_pm_suspend_in_sram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Save registers on stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) stmfd sp!, {r4 - r12, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Drain write buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mov tmp1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mcr p15, 0, tmp1, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ldr tmp1, [r0, #PM_DATA_PMC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) str tmp1, .pmc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ldr tmp1, [r0, #PM_DATA_RAMC0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) str tmp1, .sramc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ldr tmp1, [r0, #PM_DATA_RAMC1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) str tmp1, .sramc1_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ldr tmp1, [r0, #PM_DATA_MEMCTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) str tmp1, .memtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ldr tmp1, [r0, #PM_DATA_MODE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) str tmp1, .pm_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) str tmp1, .mckr_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) str tmp1, .pmc_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Both ldrne below are here to preload their address in the TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ldr tmp1, [r0, #PM_DATA_SHDWC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) str tmp1, .shdwc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) cmp tmp1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ldrne tmp2, [tmp1, #0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ldr tmp1, [r0, #PM_DATA_SFRBU]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) str tmp1, .sfrbu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cmp tmp1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ldrne tmp2, [tmp1, #0x10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Active the self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mov r0, #SRAMC_SELF_FRESH_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bl at91_sramc_self_refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ldr r0, .pm_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cmp r0, #AT91_PM_STANDBY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) beq standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cmp r0, #AT91_PM_BACKUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) beq backup_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bl at91_ulp_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) b exit_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) standby:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Wait for interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ldr pmc, .pmc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) at91_cpu_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) b exit_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) backup_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bl at91_backup_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) b exit_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) exit_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Exit the self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mov r0, #SRAMC_SELF_FRESH_EXIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bl at91_sramc_self_refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Restore registers, and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ldmfd sp!, {r4 - r12, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ENDPROC(at91_pm_suspend_in_sram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ENTRY(at91_backup_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Switch the master clock source to slow clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ldr pmc, .pmc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ldr tmp2, .mckr_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ldr tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bic tmp1, tmp1, #AT91_PMC_CSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) str tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*BUMEN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ldr r0, .sfrbu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mov tmp1, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) str tmp1, [r0, #0x10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ldr r0, .shdwc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mov tmp1, #0xA5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) add tmp1, tmp1, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) str tmp1, [r0, #0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ENDPROC(at91_backup_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .macro at91_pm_ulp0_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ldr pmc, .pmc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ldr tmp2, .pm_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ldr tmp3, .mckr_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Check if ULP0 fast variant has been requested. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cmp tmp2, #AT91_PM_ULP0_FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bne 0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Set highest prescaler for power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ldr tmp1, [pmc, tmp3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bic tmp1, tmp1, #AT91_PMC_PRES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) orr tmp1, tmp1, #AT91_PMC_PRES_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) str tmp1, [pmc, tmp3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) b 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Turn off the crystal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bic tmp1, tmp1, #AT91_PMC_MOSCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Save RC oscillator state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) str tmp1, .saved_osc_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Turn off RC oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Wait main RC disabled done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 2: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bne 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Wait for interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 1: at91_cpu_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Check if ULP0 fast variant has been requested. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cmp tmp2, #AT91_PM_ULP0_FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bne 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Set lowest prescaler for fast resume. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ldr tmp1, [pmc, tmp3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bic tmp1, tmp1, #AT91_PMC_PRES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) str tmp1, [pmc, tmp3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) b 6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 5: /* Restore RC oscillator state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ldr tmp1, .saved_osc_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) beq 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Turn on RC oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Wait main RC stabilization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 3: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) beq 3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Turn on the crystal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) orr tmp1, tmp1, #AT91_PMC_MOSCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) wait_moscrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Note: This procedure only applies on the platform which uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * the external crystal oscillator as a main clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .macro at91_pm_ulp1_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ldr pmc, .pmc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ldr tmp2, .mckr_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Save RC oscillator state and check if it is enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) str tmp1, .saved_osc_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bne 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Enable RC oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Wait main RC stabilization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 1: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) beq 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Switch the main clock source to 12-MHz RC oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bic tmp1, tmp1, #AT91_PMC_MOSCSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) wait_moscsels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Disable the crystal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bic tmp1, tmp1, #AT91_PMC_MOSCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Switch the master clock source to main clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ldr tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bic tmp1, tmp1, #AT91_PMC_CSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) str tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) orr tmp1, tmp1, #AT91_PMC_WAITMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Quirk for SAM9X60's PMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Enable the crystal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) orr tmp1, tmp1, #AT91_PMC_MOSCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) wait_moscrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Switch the master clock source to slow clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ldr tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) bic tmp1, tmp1, #AT91_PMC_CSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) str tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Switch main clock source to crystal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) orr tmp1, tmp1, #AT91_PMC_MOSCSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) wait_moscsels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Switch the master clock source to main clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ldr tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) bic tmp1, tmp1, #AT91_PMC_CSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) str tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Restore RC oscillator state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ldr tmp1, .saved_osc_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bne 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Disable RC oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ldr tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bic tmp1, tmp1, #AT91_PMC_KEY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) orr tmp1, tmp1, #AT91_PMC_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) str tmp1, [pmc, #AT91_CKGR_MOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Wait RC oscillator disable done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 4: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tst tmp1, #AT91_PMC_MOSCRCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bne 4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .macro at91_plla_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Save PLLA setting and disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ldr tmp1, .pmc_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cmp tmp1, #AT91_PMC_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) beq 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #ifdef CONFIG_SOC_SAM9X60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Save PLLA settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* save div. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mov tmp1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bic tmp2, tmp2, #0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) orr tmp1, tmp1, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* save mul. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bic tmp2, tmp2, #0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) orr tmp1, tmp1, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) str tmp1, .saved_pllar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* step 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* step 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* step 4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* step 5. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* step 7. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) b 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 1: /* Save PLLA setting and disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) str tmp1, .saved_pllar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Disable PLLA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mov tmp1, #AT91_PMC_PLLCOUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) str tmp1, [pmc, #AT91_CKGR_PLLAR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .macro at91_plla_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ldr tmp2, .saved_pllar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ldr tmp3, .pmc_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cmp tmp3, #AT91_PMC_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) beq 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #ifdef CONFIG_SOC_SAM9X60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* step 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* step 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) str tmp1, [pmc, #AT91_PMC_PLL_ACR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* step 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mov tmp3, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) bic tmp3, tmp3, #0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) orr tmp1, tmp1, tmp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) str tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* step 8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* step 9. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) bic tmp1, tmp1, #0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mov tmp3, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bic tmp3, tmp3, #0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) orr tmp1, tmp1, tmp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* step 10. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* step 11. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tst tmp1, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) beq 3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) b 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Restore PLLA setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 4: str tmp2, [pmc, #AT91_CKGR_PLLAR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Enable PLLA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tst tmp2, #(AT91_PMC_MUL & 0xff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tst tmp2, #(AT91_PMC_MUL & ~0xff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) beq 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 1: ldr tmp1, [pmc, #AT91_PMC_SR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tst tmp1, #AT91_PMC_LOCKA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) beq 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ENTRY(at91_ulp_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ldr pmc, .pmc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ldr tmp2, .mckr_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ldr tmp3, .pm_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Save Master clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ldr tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) str tmp1, .saved_mckr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Set master clock source to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * - MAINCK if using ULP0 fast variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * - slow clock, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bic tmp1, tmp1, #AT91_PMC_CSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cmp tmp3, #AT91_PM_ULP0_FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bne save_mck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) save_mck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) str tmp1, [pmc, tmp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) at91_plla_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) cmp tmp3, #AT91_PM_ULP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) beq ulp1_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) at91_pm_ulp0_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) b ulp_exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ulp1_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) at91_pm_ulp1_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) b ulp_exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ulp_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ldr pmc, .pmc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) at91_plla_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Restore master clock setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ldr tmp1, .mckr_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ldr tmp2, .saved_mckr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) str tmp2, [pmc, tmp1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) wait_mckrdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mov pc, lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ENDPROC(at91_ulp_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * void at91_sramc_self_refresh(unsigned int is_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * @input param:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * @r0: 1 - active self-refresh mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * 0 - exit self-refresh mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * register usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @r1: memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @r2: base address of the sram controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ENTRY(at91_sramc_self_refresh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ldr r1, .memtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ldr r2, .sramc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cmp r1, #AT91_MEMCTRL_MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) bne ddrc_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * at91rm9200 Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * For exiting the self-refresh mode, do nothing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * automatically exit the self-refresh mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) tst r0, #SRAMC_SELF_FRESH_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) beq exit_sramc_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Active SDRAM self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mov r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) str r3, [r2, #AT91_MC_SDRAMC_SRR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) b exit_sramc_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ddrc_sf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) cmp r1, #AT91_MEMCTRL_DDRSDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) bne sdramc_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * DDR Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tst r0, #SRAMC_SELF_FRESH_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) beq ddrc_exit_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* LPDDR1 --> force DDR2 mode during self-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ldr r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) str r3, .saved_sam9_mdr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bic r3, r3, #~AT91_DDRSDRC_MD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ldreq r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) biceq r3, r3, #AT91_DDRSDRC_MD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) streq r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Active DDRC self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ldr r3, [r2, #AT91_DDRSDRC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) str r3, .saved_sam9_lpr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) bic r3, r3, #AT91_DDRSDRC_LPCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) str r3, [r2, #AT91_DDRSDRC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* If using the 2nd ddr controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ldr r2, .sramc1_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) cmp r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) beq no_2nd_ddrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ldr r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) str r3, .saved_sam9_mdr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) bic r3, r3, #~AT91_DDRSDRC_MD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ldreq r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) biceq r3, r3, #AT91_DDRSDRC_MD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) streq r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Active DDRC self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ldr r3, [r2, #AT91_DDRSDRC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) str r3, .saved_sam9_lpr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bic r3, r3, #AT91_DDRSDRC_LPCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) str r3, [r2, #AT91_DDRSDRC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) no_2nd_ddrc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) b exit_sramc_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ddrc_exit_sf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Restore MDR in case of LPDDR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ldr r3, .saved_sam9_mdr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) str r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Restore LPR on AT91 with DDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ldr r3, .saved_sam9_lpr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) str r3, [r2, #AT91_DDRSDRC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* If using the 2nd ddr controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ldr r2, .sramc1_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cmp r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ldrne r3, .saved_sam9_mdr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) strne r3, [r2, #AT91_DDRSDRC_MDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ldrne r3, .saved_sam9_lpr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) strne r3, [r2, #AT91_DDRSDRC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) b exit_sramc_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * SDRAMC Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) sdramc_sf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tst r0, #SRAMC_SELF_FRESH_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) beq sdramc_exit_sf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Active SDRAMC self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ldr r3, [r2, #AT91_SDRAMC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) str r3, .saved_sam9_lpr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) bic r3, r3, #AT91_SDRAMC_LPCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) str r3, [r2, #AT91_SDRAMC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) sdramc_exit_sf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ldr r3, .saved_sam9_lpr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) str r3, [r2, #AT91_SDRAMC_LPR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) exit_sramc_sf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mov pc, lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ENDPROC(at91_sramc_self_refresh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .pmc_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .sramc_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .sramc1_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .shdwc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .sfrbu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .memtype:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .pm_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .mckr_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .pmc_version:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .saved_mckr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .saved_pllar:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .saved_sam9_lpr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .saved_sam9_lpr1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .saved_sam9_mdr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .saved_sam9_mdr1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .saved_osc_status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ENTRY(at91_pm_suspend_in_sram_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .word .-at91_pm_suspend_in_sram
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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