Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/lib/muldi3.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Author:     Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Created:    Oct 19, 2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Copyright:  Monta Vista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define xh r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define xl r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define yh r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define yl r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define xl r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define xh r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define yl r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define yh r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ENTRY(__muldi3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ENTRY(__aeabi_lmul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	mul	xh, yl, xh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	mla	xh, xl, yh, xh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	mov	ip, xl, lsr #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	mov	yh, yl, lsr #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	bic	xl, xl, ip, lsl #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	bic	yl, yl, yh, lsl #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	mla	xh, yh, ip, xh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	mul	yh, xl, yh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	mul	xl, yl, xl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	mul	ip, yl, ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	adds	xl, xl, yh, lsl #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	adc	xh, xh, yh, lsr #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	adds	xl, xl, ip, lsl #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	adc	xh, xh, ip, lsr #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ENDPROC(__muldi3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ENDPROC(__aeabi_lmul)