Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2015, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/opcodes-sec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/opcodes-virt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/unwind.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	 * Wrap c macros in asm macros to delay expansion until after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	 * SMCCC asm macro is expanded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.macro SMCCC_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	__SMC(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.macro SMCCC_HVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	__HVC(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	.macro SMCCC instr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) UNWIND(	.fnstart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	mov	r12, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	push	{r4-r7}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) UNWIND(	.save	{r4-r7})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	ldm	r12, {r4-r7}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	\instr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	ldr	r4, [sp, #36]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	cmp	r4, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	beq	1f			// No quirk structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ldr     r5, [r4, #ARM_SMCCC_QUIRK_ID_OFFS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	cmp     r5, #ARM_SMCCC_QUIRK_QCOM_A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	bne	1f			// No quirk present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	str	r6, [r4, #ARM_SMCCC_QUIRK_STATE_OFFS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 1:	pop	{r4-r7}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	ldr	r12, [sp, #(4 * 4)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	stm	r12, {r0-r3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	bx	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) UNWIND(	.fnend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  * void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  *		  unsigned long a3, unsigned long a4, unsigned long a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  *		  unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  *		  struct arm_smccc_quirk *quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ENTRY(__arm_smccc_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	SMCCC SMCCC_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ENDPROC(__arm_smccc_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  * void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  *		  unsigned long a3, unsigned long a4, unsigned long a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  *		  unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  *		  struct arm_smccc_quirk *quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ENTRY(__arm_smccc_hvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	SMCCC SMCCC_HVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ENDPROC(__arm_smccc_hvc)