^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/glue-cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/glue-proc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Implementation of MPIDR hash algorithm through shifting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * and OR'ing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * @dst: register containing hash result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * @rs0: register containing affinity level 0 bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @rs1: register containing affinity level 1 bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * @rs2: register containing affinity level 2 bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @mpidr: register containing MPIDR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @mask: register containing MPIDR mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Pseudo C-code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *u32 dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * u32 aff0, aff1, aff2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * u32 mpidr_masked = mpidr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * aff0 = mpidr_masked & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * aff1 = mpidr_masked & 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * aff2 = mpidr_masked & 0xff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Input registers: rs0, rs1, rs2, mpidr, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Output register: dst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Note: input and output registers must be disjoint register sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) and \mpidr, \mpidr, \mask @ mask out MPIDR bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) and \dst, \mpidr, #0xff @ mask=aff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ARM( mov \dst, \dst, lsr \rs0 ) @ dst=aff0>>rs0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) THUMB( lsr \dst, \dst, \rs0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) and \mask, \mpidr, #0xff00 @ mask = aff1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ARM( orr \dst, \dst, \mask, lsr \rs1 ) @ dst|=(aff1>>rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) THUMB( lsr \mask, \mask, \rs1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) THUMB( orr \dst, \dst, \mask )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) and \mask, \mpidr, #0xff0000 @ mask = aff2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ARM( orr \dst, \dst, \mask, lsr \rs2 ) @ dst|=(aff2>>rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) THUMB( lsr \mask, \mask, \rs2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) THUMB( orr \dst, \dst, \mask )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Save CPU state for a suspend. This saves the CPU general purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * registers, and allocates space on the kernel stack to save the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * specific registers and some other data for resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * r0 = suspend function arg0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * r1 = suspend function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * r2 = MPIDR value the resuming CPU will use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ENTRY(__cpu_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) stmfd sp!, {r4 - r11, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef MULTI_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ldr r10, =processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ldr r4, =cpu_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mov r5, sp @ current virtual SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) sub sp, sp, r4 @ allocate CPU state on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ldr r3, =sleep_save_sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) stmfd sp!, {r0, r1} @ save suspend func arg and pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ldr r3, [r3, #SLEEP_SAVE_SP_VIRT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ALT_SMP(ldr r0, =mpidr_hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ALT_UP_B(1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* This ldmia relies on the memory layout of the mpidr_hash struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ldmia r0, {r1, r6-r8} @ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) compute_mpidr_hash r0, r6, r7, r8, r2, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) add r3, r3, r0, lsl #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 1: mov r2, r5 @ virtual SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mov r1, r4 @ size of save block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) add r0, sp, #8 @ pointer to save block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bl __cpu_suspend_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) badr lr, cpu_suspend_abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ldmfd sp!, {r0, pc} @ call suspend fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ENDPROC(__cpu_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .ltorg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) cpu_suspend_abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) teq r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) moveq r0, #1 @ force non-zero value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mov sp, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ldmfd sp!, {r4 - r11, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ENDPROC(cpu_suspend_abort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * r0 = control register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pushsection .idmap.text,"ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ENTRY(cpu_resume_mmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ldr r3, =cpu_resume_after_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) instr_sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mrc p15, 0, r0, c0, c0, 0 @ read id reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) instr_sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mov r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mov r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret r3 @ jump to virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ENDPROC(cpu_resume_mmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) cpu_resume_after_mmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bl cpu_init @ restore the und/abt/irq banked regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mov r0, #0 @ return zero on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ldmfd sp!, {r4 - r11, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ENDPROC(cpu_resume_after_mmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_MCPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) THUMB( .thumb )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ENTRY(cpu_resume_no_hyp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ARM_BE8(setend be) @ ensure we are in BE mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) b no_hyp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ENTRY(cpu_resume_arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) THUMB( badr r9, 1f ) @ Kernel is entered in ARM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) THUMB( .thumb ) @ switch to Thumb now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) THUMB(1: )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ENTRY(cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ARM_BE8(setend be) @ ensure we are in BE mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #ifdef CONFIG_ARM_VIRT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bl __hyp_stub_install_secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) safe_svcmode_maskall r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) no_hyp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mov r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ALT_UP_B(1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) adr r2, mpidr_hash_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ldr r3, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) add r2, r2, r3 @ r2 = struct mpidr_hash phys address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * This ldmia relies on the memory layout of the mpidr_hash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * struct mpidr_hash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ldmia r2, { r3-r6 } @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) compute_mpidr_hash r1, r4, r5, r6, r0, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) adr r0, _sleep_save_sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ldr r2, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) add r0, r0, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ldr r0, [r0, #SLEEP_SAVE_SP_PHYS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ldr r0, [r0, r1, lsl #2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) @ load phys pgd, stack, resume fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ARM( ldmia r0!, {r1, sp, pc} )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) THUMB( ldmia r0!, {r1, r2, r3} )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) THUMB( mov sp, r2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) THUMB( bx r3 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ENDPROC(cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ENDPROC(cpu_resume_arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #ifdef CONFIG_MCPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ENDPROC(cpu_resume_no_hyp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) _sleep_save_sp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .long sleep_save_sp - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mpidr_hash_ptr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .long mpidr_hash - . @ mpidr_hash struct offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .type sleep_save_sp, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ENTRY(sleep_save_sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .space SLEEP_SAVE_SP_SZ @ struct sleep_save_sp
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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