^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/kernel/setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-2001 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/efi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/utsname.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/initrd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kexec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/libfdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/psci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/unified.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/efi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/early_ioremap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/procinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/psci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/cachetype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/xen/hypervisor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <asm/unwind.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <asm/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <asm/virt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "atags.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) char fpe_type[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int __init fpe_setup(char *line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) memcpy(fpe_type, line, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __setup("fpe=", fpe_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) extern void init_default_cache_policy(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) extern void paging_init(const struct machine_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern void early_mm_init(const struct machine_desc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern void adjust_lowmem_bounds(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) extern enum reboot_mode reboot_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern void setup_dma_zone(const struct machine_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int processor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EXPORT_SYMBOL(processor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int __machine_arch_type __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) EXPORT_SYMBOL(__machine_arch_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int cacheid __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EXPORT_SYMBOL(cacheid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int __atags_pointer __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int system_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EXPORT_SYMBOL(system_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const char *system_serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) EXPORT_SYMBOL(system_serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int system_serial_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EXPORT_SYMBOL(system_serial_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int system_serial_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) EXPORT_SYMBOL(system_serial_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int elf_hwcap __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) EXPORT_SYMBOL(elf_hwcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int elf_hwcap2 __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EXPORT_SYMBOL(elf_hwcap2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef MULTI_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct processor processor __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct processor *cpu_vtable[NR_CPUS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [0] = &processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifdef MULTI_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct cpu_tlb_fns cpu_tlb __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #ifdef MULTI_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct cpu_user_fns cpu_user __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef MULTI_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct cpu_cache_fns cpu_cache __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_OUTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct outer_cache_fns outer_cache __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EXPORT_SYMBOL(outer_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Cached cpu_architecture() result for use by assembler code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * C code should use the cpu_architecture() function instead of accessing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * variable directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct stack {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 irq[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 abt[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 und[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 fiq[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifndef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct stack stacks[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) char elf_platform[ELF_PLATFORM_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) EXPORT_SYMBOL(elf_platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const char *cpu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const char *machine_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static char __initdata cmd_line[COMMAND_LINE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct machine_desc *machine_desc __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ENDIANNESS ((char)endian_test.l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Standard memory resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct resource mem_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "Video RAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .end = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "Kernel code",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .end = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .flags = IORESOURCE_SYSTEM_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "Kernel data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .end = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .flags = IORESOURCE_SYSTEM_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define video_ram mem_res[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define kernel_code mem_res[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define kernel_data mem_res[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct resource io_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .name = "reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .start = 0x3bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .end = 0x3be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .flags = IORESOURCE_IO | IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .start = 0x378,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .end = 0x37f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .flags = IORESOURCE_IO | IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .start = 0x278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .end = 0x27f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .flags = IORESOURCE_IO | IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define lp0 io_res[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define lp1 io_res[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define lp2 io_res[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char *proc_arch[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "undefined/unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "4T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "5T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "5TE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "5TEJ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "6TEJ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "7M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "?(12)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "?(13)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "?(14)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "?(15)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "?(16)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "?(17)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #ifdef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int __get_cpu_architecture(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return CPU_ARCH_ARMv7M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int __get_cpu_architecture(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int cpu_arch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if ((read_cpuid_id() & 0x0008f000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cpu_arch = CPU_ARCH_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cpu_arch = (read_cpuid_id() >> 16) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (cpu_arch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cpu_arch += CPU_ARCH_ARMv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Revised CPUID format. Read the Memory Model Feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Register 0 and check for VMSAv7 or PMSAv7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (mmfr0 & 0x000000f0) >= 0x00000030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cpu_arch = CPU_ARCH_ARMv7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (mmfr0 & 0x000000f0) == 0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cpu_arch = CPU_ARCH_ARMv6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cpu_arch = CPU_ARCH_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cpu_arch = CPU_ARCH_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return cpu_arch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int __pure cpu_architecture(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return __cpu_architecture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int cpu_has_aliasing_icache(unsigned int arch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int aliasing_icache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int id_reg, num_sets, line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* PIPT caches never alias. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (icache_is_pipt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* arch specifies the register format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) switch (arch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case CPU_ARCH_ARMv7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) set_csselr(CSSELR_ICACHE | CSSELR_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) id_reg = read_ccsidr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) line_size = 4 << ((id_reg & 0x7) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) num_sets = ((id_reg >> 13) & 0x7fff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case CPU_ARCH_ARMv6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) aliasing_icache = read_cpuid_cachetype() & (1 << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* I-cache aliases will be handled by D-cache aliasing code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) aliasing_icache = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return aliasing_icache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void __init cacheid_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int arch = cpu_architecture();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (arch >= CPU_ARCH_ARMv6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int cachetype = read_cpuid_cachetype();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cacheid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } else if ((cachetype & (7 << 29)) == 4 << 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* ARMv7 register format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) arch = CPU_ARCH_ARMv7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cacheid = CACHEID_VIPT_NONALIASING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) switch (cachetype & (3 << 14)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case (1 << 14):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cacheid |= CACHEID_ASID_TAGGED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case (3 << 14):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cacheid |= CACHEID_PIPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) arch = CPU_ARCH_ARMv6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (cachetype & (1 << 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cacheid = CACHEID_VIPT_ALIASING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cacheid = CACHEID_VIPT_NONALIASING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (cpu_has_aliasing_icache(arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cacheid |= CACHEID_VIPT_I_ALIASING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cacheid = CACHEID_VIVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pr_info("CPU: %s data cache, %s instruction cache\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cache_is_vivt() ? "VIVT" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cache_is_vipt_aliasing() ? "VIPT aliasing" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cache_is_vivt() ? "VIVT" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) icache_is_vipt_aliasing() ? "VIPT aliasing" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) icache_is_pipt() ? "PIPT" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * These functions re-use the assembly code in head.S, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * already provide the required functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) extern struct proc_info_list *lookup_processor_type(unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void __init early_print(const char *str, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) extern void printascii(const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) char buf[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) va_list ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) va_start(ap, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) vsnprintf(buf, sizeof(buf), str, ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) va_end(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #ifdef CONFIG_DEBUG_LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) printascii(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) printk("%s", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #ifdef CONFIG_ARM_PATCH_IDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline u32 __attribute_const__ sdiv_instruction(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* "sdiv r0, r0, r1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 insn = __opcode_thumb32_compose(0xfb90, 0xf0f1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return __opcode_to_mem_thumb32(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* "sdiv r0, r0, r1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return __opcode_to_mem_arm(0xe710f110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static inline u32 __attribute_const__ udiv_instruction(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* "udiv r0, r0, r1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 insn = __opcode_thumb32_compose(0xfbb0, 0xf0f1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return __opcode_to_mem_thumb32(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* "udiv r0, r0, r1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return __opcode_to_mem_arm(0xe730f110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static inline u32 __attribute_const__ bx_lr_instruction(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* "bx lr; nop" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 insn = __opcode_thumb32_compose(0x4770, 0x46c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return __opcode_to_mem_thumb32(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* "bx lr" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return __opcode_to_mem_arm(0xe12fff1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void __init patch_aeabi_idiv(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) extern void __aeabi_uidiv(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) extern void __aeabi_idiv(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) uintptr_t fn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mask = IS_ENABLED(CONFIG_THUMB2_KERNEL) ? HWCAP_IDIVT : HWCAP_IDIVA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!(elf_hwcap & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pr_info("CPU: div instructions available: patching division code\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) fn_addr = ((uintptr_t)&__aeabi_uidiv) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) asm ("" : "+g" (fn_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ((u32 *)fn_addr)[0] = udiv_instruction();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ((u32 *)fn_addr)[1] = bx_lr_instruction();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) flush_icache_range(fn_addr, fn_addr + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fn_addr = ((uintptr_t)&__aeabi_idiv) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) asm ("" : "+g" (fn_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ((u32 *)fn_addr)[0] = sdiv_instruction();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ((u32 *)fn_addr)[1] = bx_lr_instruction();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) flush_icache_range(fn_addr, fn_addr + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline void patch_aeabi_idiv(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void __init cpuid_init_hwcaps(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 isar5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (cpu_architecture() < CPU_ARCH_ARMv7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (block >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) elf_hwcap |= HWCAP_IDIVA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (block >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) elf_hwcap |= HWCAP_IDIVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* LPAE implies atomic ldrd/strd instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (block >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) elf_hwcap |= HWCAP_LPAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* check for supported v8 Crypto instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) block = cpuid_feature_extract_field(isar5, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (block >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) elf_hwcap2 |= HWCAP2_PMULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (block >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) elf_hwcap2 |= HWCAP2_AES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) block = cpuid_feature_extract_field(isar5, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (block >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) elf_hwcap2 |= HWCAP2_SHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) block = cpuid_feature_extract_field(isar5, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (block >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) elf_hwcap2 |= HWCAP2_SHA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) block = cpuid_feature_extract_field(isar5, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (block >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) elf_hwcap2 |= HWCAP2_CRC32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static void __init elf_hwcap_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned id = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * HWCAP_TLS is available only on 1136 r1p0 and later,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * see also kuser_get_tls_init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ((id >> 20) & 3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) elf_hwcap &= ~HWCAP_TLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Verify if CPUID scheme is implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if ((id & 0x000f0000) != 0x000f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * If the CPU supports LDREX/STREX and LDREXB/STREXB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * avoid advertising SWP; it may not be atomic with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * multiprocessing cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cpuid_feature_extract(CPUID_EXT_ISAR4, 20) >= 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) elf_hwcap &= ~HWCAP_SWP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * cpu_init - initialise one CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * cpu_init sets up the per-CPU stacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void notrace cpu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #ifndef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct stack *stk = &stacks[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (cpu >= NR_CPUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pr_crit("CPU%u: bad primary CPU number\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * This only works on resume and secondary cores. For booting on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) set_my_cpu_offset(per_cpu_offset(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cpu_proc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * Define the placement constraint for the inline asm directive below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * In Thumb-2, msr with an immediate value is not allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #ifdef CONFIG_THUMB2_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PLC_l "l"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define PLC_r "r"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define PLC_l "I"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define PLC_r "I"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * setup stacks for re-entrant exception handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __asm__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "msr cpsr_c, %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "add r14, %0, %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "mov sp, r14\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "msr cpsr_c, %3\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "add r14, %0, %4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "mov sp, r14\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "msr cpsr_c, %5\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "add r14, %0, %6\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "mov sp, r14\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "msr cpsr_c, %7\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) "add r14, %0, %8\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "mov sp, r14\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "msr cpsr_c, %9"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) : "r" (stk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "I" (offsetof(struct stack, irq[0])),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "I" (offsetof(struct stack, abt[0])),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "I" (offsetof(struct stack, und[0])),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "I" (offsetof(struct stack, fiq[0])),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) : "r14");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void __init smp_setup_processor_id(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cpu_logical_map(0) = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (i = 1; i < nr_cpu_ids; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cpu_logical_map(i) = i == cpu ? 0 : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * clear __my_cpu_offset on boot CPU to avoid hang caused by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * using percpu variable early, for example, lockdep will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * access percpu variable inside lock_release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) set_my_cpu_offset(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct mpidr_hash mpidr_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * level in order to build a linear index from an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * MPIDR value. Resulting algorithm is a collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * free hash carried out through shifting and ORing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static void __init smp_build_mpidr_hash(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 i, affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 fs[3], bits[3], ls, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Pre-scan the list of MPIDRS and filter out bits that do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * not contribute to affinity levels, ie they never toggle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) for_each_possible_cpu(i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pr_debug("mask of set bits 0x%x\n", mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Find and stash the last and first bit set at all affinity levels to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * check how many bits are required to represent them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) affinity = MPIDR_AFFINITY_LEVEL(mask, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Find the MSB bit and LSB bits position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * to determine how many bits are required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * to express the affinity level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ls = fls(affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) fs[i] = affinity ? ffs(affinity) - 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) bits[i] = ls - fs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * An index can be created from the MPIDR by isolating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * significant bits at each affinity level and by shifting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * them in order to compress the 24 bits values space to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * compressed set of values. This is equivalent to hashing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * the MPIDR through shifting and ORing. It is a collision free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * hash though not minimal since some levels might contain a number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * of CPUs that is not an exact power of 2 and their bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mpidr_hash.shift_aff[0] = fs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (bits[1] + bits[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mpidr_hash.mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mpidr_hash.bits = bits[2] + bits[1] + bits[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mpidr_hash.shift_aff[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mpidr_hash.shift_aff[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mpidr_hash.shift_aff[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mpidr_hash.mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) mpidr_hash.bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * 4x is an arbitrary value used to warn on a hash table much bigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * than expected on most systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (mpidr_hash_size() > 4 * num_possible_cpus())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pr_warn("Large number of MPIDR hash buckets detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) sync_cache_w(&mpidr_hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * locate processor in the list of supported processor types. The linker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * builds this table for us from the entries in arch/arm/mm/proc-*.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct proc_info_list *lookup_processor(u32 midr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct proc_info_list *list = lookup_processor_type(midr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pr_err("CPU%u: configuration botched (ID %08x), CPU halted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) smp_processor_id(), midr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* can't use cpu_relax() here as it may require MMU setup */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static void __init setup_processor(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned int midr = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct proc_info_list *list = lookup_processor(midr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) cpu_name = list->cpu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) __cpu_architecture = __get_cpu_architecture();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) init_proc_vtable(list->proc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #ifdef MULTI_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) cpu_tlb = *list->tlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #ifdef MULTI_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cpu_user = *list->user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #ifdef MULTI_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) cpu_cache = *list->cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) list->cpu_name, midr, midr & 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) proc_arch[cpu_architecture()], get_cr());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) list->arch_name, ENDIANNESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) list->elf_name, ENDIANNESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) elf_hwcap = list->elf_hwcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cpuid_init_hwcaps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) patch_aeabi_idiv();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #ifndef CONFIG_ARM_THUMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) init_default_cache_policy(list->__cpu_mm_mmu_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) erratum_a15_798181_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) elf_hwcap_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cacheid_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) cpu_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) void __init dump_machine_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) const struct machine_desc *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) early_print("Available machine support:\n\nID (hex)\tNAME\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) for_each_machine_desc(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) early_print("%08x\t%s\n", p->nr, p->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) early_print("\nPlease check your kernel config and/or bootloader.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) while (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* can't use cpu_relax() here as it may require MMU setup */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int __init arm_add_memory(u64 start, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u64 aligned_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Ensure that start/size are aligned to a page boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * Size is rounded down, start is rounded up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) aligned_start = PAGE_ALIGN(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (aligned_start > start + size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) size -= aligned_start - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #ifndef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (aligned_start > ULONG_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) (long long)start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (aligned_start + size > ULONG_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) (long long)start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * To ensure bank->start + bank->size is representable in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * This means we lose a page after masking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) size = ULONG_MAX - aligned_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (aligned_start < PHYS_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (aligned_start + size <= PHYS_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) aligned_start, aligned_start + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) aligned_start, (u64)PHYS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) size -= PHYS_OFFSET - aligned_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) aligned_start = PHYS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) start = aligned_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * Check whether this memory region has non-zero size or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * invalid node number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) memblock_add(start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Pick out the memory size. We look for mem=size@start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * where start and size are "size[KkMm]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int __init early_mem(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int usermem __initdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) char *endp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * If the user specifies memory size, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * blow away any automatically generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (usermem == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) usermem = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) memblock_remove(memblock_start_of_DRAM(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) memblock_end_of_DRAM() - memblock_start_of_DRAM());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) start = PHYS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) size = memparse(p, &endp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (*endp == '@')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) start = memparse(endp + 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) arm_add_memory(start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) early_param("mem", early_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void __init request_standard_resources(const struct machine_desc *mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) phys_addr_t start, end, res_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u64 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) kernel_code.start = virt_to_phys(_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) kernel_code.end = virt_to_phys(__init_begin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) kernel_data.start = virt_to_phys(_sdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) kernel_data.end = virt_to_phys(_end - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) for_each_mem_range(i, &start, &end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned long boot_alias_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * In memblock, end points to the first byte after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * range while in resourses, end points to the last byte in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * the range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) res_end = end - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * Some systems have a special memory alias which is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * used for booting. We need to advertise this region to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * kexec-tools so they know where bootable RAM is located.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) boot_alias_start = phys_to_idmap(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (arm_has_idmap_alias() && boot_alias_start != IDMAP_INVALID_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) panic("%s: Failed to allocate %zu bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __func__, sizeof(*res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) res->name = "System RAM (boot alias)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) res->start = boot_alias_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) res->end = phys_to_idmap(res_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) request_resource(&iomem_resource, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) panic("%s: Failed to allocate %zu bytes\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) sizeof(*res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) res->name = "System RAM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) res->start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) res->end = res_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) request_resource(&iomem_resource, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (kernel_code.start >= res->start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) kernel_code.end <= res->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) request_resource(res, &kernel_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (kernel_data.start >= res->start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) kernel_data.end <= res->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) request_resource(res, &kernel_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (mdesc->video_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) video_ram.start = mdesc->video_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) video_ram.end = mdesc->video_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) request_resource(&iomem_resource, &video_ram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Some machines don't have the possibility of ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * possessing lp0, lp1 or lp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (mdesc->reserve_lp0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) request_resource(&ioport_resource, &lp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (mdesc->reserve_lp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) request_resource(&ioport_resource, &lp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (mdesc->reserve_lp2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) request_resource(&ioport_resource, &lp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) defined(CONFIG_EFI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct screen_info screen_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .orig_video_lines = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .orig_video_cols = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .orig_video_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .orig_video_ega_bx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .orig_video_isVGA = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .orig_video_points = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int __init customize_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * customizes platform devices, or adds new ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * On DT based machines, we fall back to populating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * machine from the device tree, if no callback is provided,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * otherwise we would always need an init_machine callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (machine_desc->init_machine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) machine_desc->init_machine();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) arch_initcall(customize_machine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int __init init_machine_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct device_node *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (machine_desc->init_late)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) machine_desc->init_late();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) root = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (root) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = of_property_read_string(root, "serial-number",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) &system_serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) system_serial = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!system_serial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) system_serial = kasprintf(GFP_KERNEL, "%08x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) system_serial_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) system_serial_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) late_initcall(init_machine_late);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #ifdef CONFIG_KEXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * The crash region must be aligned to 128MB to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * zImage relocating below the reserved region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define CRASH_ALIGN (128 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static inline unsigned long long get_total_mem(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned long total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) total = max_low_pfn - min_low_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return total << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * reserve_crashkernel() - reserves memory are for crash kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * This function reserves memory area given in "crashkernel=" kernel command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * line parameter. The memory reserved is used by a dump capture kernel when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * primary kernel is crashing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static void __init reserve_crashkernel(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned long long crash_size, crash_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned long long total_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) total_mem = get_total_mem();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = parse_crashkernel(boot_command_line, total_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) &crash_size, &crash_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (crash_base <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned long long crash_max = idmap_to_phys((u32)~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unsigned long long lowmem_max = __pa(high_memory - 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (crash_max > lowmem_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) crash_max = lowmem_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) crash_base = memblock_find_in_range(CRASH_ALIGN, crash_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) crash_size, CRASH_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (!crash_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pr_err("crashkernel reservation failed - No suitable area found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) unsigned long long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) start = memblock_find_in_range(crash_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) crash_base + crash_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) crash_size, SECTION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (start != crash_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pr_err("crashkernel reservation failed - memory is in use.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = memblock_reserve(crash_base, crash_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) (unsigned long)crash_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) (unsigned long)(crash_size >> 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) (unsigned long)(crash_base >> 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) (unsigned long)(total_mem >> 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* The crashk resource must always be located in normal mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) crashk_res.start = crash_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) crashk_res.end = crash_base + crash_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) insert_resource(&iomem_resource, &crashk_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (arm_has_idmap_alias()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * If we have a special RAM alias for use at boot, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * need to advertise to kexec tools where the alias is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static struct resource crashk_boot_res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .name = "Crash kernel (boot alias)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .flags = IORESOURCE_BUSY | IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) crashk_boot_res.start = phys_to_idmap(crash_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) crashk_boot_res.end = crashk_boot_res.start + crash_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) insert_resource(&iomem_resource, &crashk_boot_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static inline void reserve_crashkernel(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #endif /* CONFIG_KEXEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) void __init hyp_mode_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #ifdef CONFIG_ARM_VIRT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) sync_boot_mode();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (is_hyp_mode_available()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pr_info("CPU: All CPU(s) started in HYP mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pr_info("CPU: Virtualization extensions available.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) } else if (is_hyp_mode_mismatched()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) __boot_cpu_mode & MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) pr_info("CPU: All CPU(s) started in SVC mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static void (*__arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int arm_restart(struct notifier_block *nb, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) __arm_pm_restart(action, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static struct notifier_block arm_restart_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .notifier_call = arm_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .priority = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) void __init setup_arch(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) const struct machine_desc *mdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) void *atags_vaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (__atags_pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) atags_vaddr = FDT_VIRT_BASE(__atags_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) setup_processor();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (atags_vaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) mdesc = setup_machine_fdt(atags_vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) memblock_reserve(__atags_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) fdt_totalsize(atags_vaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) mdesc = setup_machine_tags(atags_vaddr, __machine_arch_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (!mdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) early_print("\nError: invalid dtb and unrecognized/unsupported machine ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) early_print(" r1=0x%08x, r2=0x%08x\n", __machine_arch_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) __atags_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (__atags_pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) early_print(" r2[]=%*ph\n", 16, atags_vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dump_machine_table();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) machine_desc = mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) machine_name = mdesc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dump_stack_set_arch_desc("%s", mdesc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (mdesc->reboot_mode != REBOOT_HARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) reboot_mode = mdesc->reboot_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) init_mm.start_code = (unsigned long) _text;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) init_mm.end_code = (unsigned long) _etext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) init_mm.end_data = (unsigned long) _edata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) init_mm.brk = (unsigned long) _end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* populate cmd_line too for later use, preserving boot_command_line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) *cmdline_p = cmd_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) early_fixmap_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) early_ioremap_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) parse_early_param();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) early_mm_init(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) setup_dma_zone(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) xen_early_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) efi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * Make sure the calculation for lowmem/highmem is set appropriately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * before reserving/allocating any mmeory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) adjust_lowmem_bounds();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) arm_memblock_init(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Memory may have been removed so recalculate the bounds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) adjust_lowmem_bounds();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) early_ioremap_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) paging_init(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) request_standard_resources(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (mdesc->restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) __arm_pm_restart = mdesc->restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) register_restart_handler(&arm_restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) unflatten_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) arm_dt_init_cpu_maps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) psci_dt_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (is_smp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!mdesc->smp_init || !mdesc->smp_init()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (psci_smp_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) smp_set_ops(&psci_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) else if (mdesc->smp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) smp_set_ops(mdesc->smp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) smp_init_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) smp_build_mpidr_hash();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (!is_smp())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) hyp_mode_check();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) reserve_crashkernel();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) handle_arch_irq = mdesc->handle_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #ifdef CONFIG_VT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #if defined(CONFIG_VGA_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) conswitchp = &vga_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (mdesc->init_early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mdesc->init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static int __init topology_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) cpuinfo->cpu.hotpluggable = platform_can_hotplug_cpu(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) register_cpu(&cpuinfo->cpu, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) subsys_initcall(topology_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #ifdef CONFIG_HAVE_PROC_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int __init proc_cpu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct proc_dir_entry *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) res = proc_mkdir("cpu", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) fs_initcall(proc_cpu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static const char *hwcap_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "swp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) "thumb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "26bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) "fastmult",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) "fpa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) "vfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) "edsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "java",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) "iwmmxt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "crunch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "thumbee",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) "neon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "vfpv3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) "vfpv3d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "tls",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) "vfpv4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) "idiva",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) "idivt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) "vfpd32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) "lpae",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) "evtstrm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static const char *hwcap2_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) "aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "pmull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) "sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) "sha2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) "crc32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static int c_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u32 cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) for_each_online_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * glibc reads /proc/cpuinfo to determine the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * online processors, looking for lines beginning with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * "processor". Give glibc what it expects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) seq_printf(m, "processor\t: %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) seq_printf(m, "model name\t: %s rev %d (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) cpu_name, cpuid & 15, elf_platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #if defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) loops_per_jiffy / (500000/HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) (loops_per_jiffy / (5000/HZ)) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* dump out the processor features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) seq_puts(m, "Features\t: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) for (j = 0; hwcap_str[j]; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (elf_hwcap & (1 << j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) seq_printf(m, "%s ", hwcap_str[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) for (j = 0; hwcap2_str[j]; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (elf_hwcap2 & (1 << j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) seq_printf(m, "%s ", hwcap2_str[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) seq_printf(m, "CPU architecture: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) proc_arch[cpu_architecture()]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if ((cpuid & 0x0008f000) == 0x00000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* pre-ARM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if ((cpuid & 0x0008f000) == 0x00007000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* ARM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) seq_printf(m, "CPU variant\t: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) (cpuid >> 16) & 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* post-ARM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) seq_printf(m, "CPU variant\t: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) (cpuid >> 20) & 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) seq_printf(m, "CPU part\t: 0x%03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) (cpuid >> 4) & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) seq_printf(m, "Hardware\t: %s\n", machine_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) seq_printf(m, "Revision\t: %04x\n", system_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) seq_printf(m, "Serial\t\t: %s\n", system_serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static void *c_start(struct seq_file *m, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return *pos < 1 ? (void *)1 : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static void *c_next(struct seq_file *m, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) const struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .start = c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .next = c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .stop = c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .show = c_show
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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