Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/kernel/opcodes.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  A32 condition code lookup feature moved from nwfpe/fpopcode.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/opcodes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ARM_OPCODE_CONDITION_UNCOND 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * condition code lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * bit position in short is condition code: NZCV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static const unsigned short cc_map[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	0xF0F0,			/* EQ == Z set            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	0x0F0F,			/* NE                     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	0xCCCC,			/* CS == C set            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	0x3333,			/* CC                     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	0xFF00,			/* MI == N set            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	0x00FF,			/* PL                     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	0xAAAA,			/* VS == V set            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	0x5555,			/* VC                     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	0x0C0C,			/* HI == C set && Z clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	0xF3F3,			/* LS == C clear || Z set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	0xAA55,			/* GE == (N==V)           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	0x55AA,			/* LT == (N!=V)           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	0x0A05,			/* GT == (!Z && (N==V))   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	0xF5FA,			/* LE == (Z || (N!=V))    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	0xFFFF,			/* AL always              */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	0			/* NV                     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * ARM_OPCODE_CONDTEST_FAIL   - if condition fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * ARM_OPCODE_CONDTEST_PASS   - if condition passes (including AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * ARM_OPCODE_CONDTEST_UNCOND - if NV condition, or separate unconditional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  *                              opcode space from v5 onwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * Code that tests whether a conditional instruction would pass its condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  * check should check that return value == ARM_OPCODE_CONDTEST_PASS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  * Code that tests if a condition means that the instruction would be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  * (regardless of conditional or unconditional) should instead check that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * return value != ARM_OPCODE_CONDTEST_FAIL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	u32 cc_bits  = opcode >> 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u32 psr_cond = psr >> 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		if ((cc_map[cc_bits] >> (psr_cond)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			ret = ARM_OPCODE_CONDTEST_PASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			ret = ARM_OPCODE_CONDTEST_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		ret = ARM_OPCODE_CONDTEST_UNCOND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) EXPORT_SYMBOL_GPL(arm_check_condition);