^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/kernel/head.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1994-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2003 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Kernel startup code for all 32-bit CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include CONFIG_DEBUG_LL_INCLUDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * swapper_pg_dir is the virtual address of the initial page table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * the least significant 16 bits to be 0x8000, but we could probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #error KERNEL_RAM_VADDR must start at 0xXXXX8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* LPAE requires an additional page for the PGD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PG_DIR_SIZE 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PMD_ORDER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PG_DIR_SIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PMD_ORDER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .globl swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .macro pgtbl, rd, phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) add \rd, \phys, #(TEXT_OFFSET & 0xffff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) add \rd, \rd, #(TEXT_OFFSET & 0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) sub \rd, \rd, #PG_DIR_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Kernel startup entry point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * This is normally called from the decompressor code. The requirements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * r1 = machine nr, r2 = atags or dtb pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * This code is mostly position independent, so if you link the kernel at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 0xc0008000, you call this at __pa(0xc0008000).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * See linux/arch/arm/tools/mach-types for the complete list of machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * numbers for r1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * We're trying to keep crap to a minimum; DO NOT add any machine specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * crap here - that's what the boot loader (or in extreme, well justified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * circumstances, zImage) is for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ENTRY(stext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ARM_BE8(setend be ) @ ensure we are in BE8 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) THUMB( badr r9, 1f ) @ Kernel is always entered in ARM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) THUMB( .thumb ) @ switch to Thumb now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) THUMB(1: )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_ARM_VIRT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bl __hyp_stub_install
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) @ ensure svc mode and all interrupts masked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) safe_svcmode_maskall r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mrc p15, 0, r9, c0, c0 @ get processor id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bl __lookup_processor_type @ r5=procinfo r9=cpuid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) movs r10, r5 @ invalid processor (r5=0)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) THUMB( it eq ) @ force fixup-able long branch encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) beq __error_p @ yes, error 'p'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) and r3, r3, #0xf @ extract VMSA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cmp r3, #5 @ long-descriptor translation table format?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) THUMB( it lo ) @ force fixup-able long branch encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) blo __error_lpae @ only classic page table format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifndef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) adr r3, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ldmia r3, {r4, r8}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) add r8, r8, r4 @ PHYS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * r1 = machine no, r2 = atags or dtb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * r8 = phys_offset, r9 = cpuid, r10 = procinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bl __vet_atags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #ifdef CONFIG_SMP_ON_UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bl __fixup_smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bl __fixup_pv_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bl __create_page_tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The following calls CPU specific code in a position independent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * xxx_proc_info structure selected by __lookup_processor_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * The processor init function will be called with:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * r1 - machine type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * r2 - boot data (atags/dt) pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * r4 - translation table base (low word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * r5 - translation table base (high word, if LPAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * r8 - translation table base 1 (pfn if LPAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * r9 - cpuid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * r13 - virtual address for __enable_mmu -> __turn_mmu_on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * On return, the CPU will be ready for the MMU to be turned on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * r0 will hold the CPU control register value, r1, r2, r4, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * r9 will be preserved. r5 will also be preserved if LPAE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ldr r13, =__mmap_switched @ address to jump to after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) @ mmu has been enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) badr lr, 1f @ return (PIC) address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mov r5, #0 @ high TTBR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mov r8, r4, lsr #12 @ TTBR1 is swapper_pg_dir pfn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mov r8, r4 @ set TTBR1 to swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ldr r12, [r10, #PROCINFO_INITFUNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) add r12, r12, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 1: b __enable_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ENDPROC(stext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .ltorg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifndef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 2: .long .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .long PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Setup the initial page tables. We only setup the barest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * amount which are required to get the kernel running, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * generally means mapping in the kernel code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * r8 = phys_offset, r9 = cpuid, r10 = procinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * r0, r3, r5-r7 corrupted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * r4 = physical page table address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __create_page_tables:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pgtbl r4, r8 @ page table address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Clear the swapper page table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mov r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mov r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) add r6, r0, #PG_DIR_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 1: str r3, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) str r3, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) str r3, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) str r3, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) teq r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bne 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Build the PGD table (first level) to point to the PMD table. A PGD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * entry is 64-bit wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mov r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) add r3, r4, #0x1000 @ first PMD table address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) orr r3, r3, #3 @ PGD block type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mov r6, #4 @ PTRS_PER_PGD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_CPU_ENDIAN_BE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) str r7, [r0], #4 @ set top PGD entry bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) str r3, [r0], #4 @ set bottom PGD entry bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) str r3, [r0], #4 @ set bottom PGD entry bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) str r7, [r0], #4 @ set top PGD entry bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) add r3, r3, #0x1000 @ next PMD table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) subs r6, r6, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bne 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) add r4, r4, #0x1000 @ point to the PMD tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #ifdef CONFIG_CPU_ENDIAN_BE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) add r4, r4, #4 @ we only write the bottom word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Create identity mapping to cater for __enable_mmu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * This identity mapping will be removed by paging_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) adr r0, __turn_mmu_on_loc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ldmia r0, {r3, r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sub r0, r0, r3 @ virt->phys offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) add r5, r5, r0 @ phys __turn_mmu_on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) add r6, r6, r0 @ phys __turn_mmu_on_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mov r5, r5, lsr #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mov r6, r6, lsr #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cmp r5, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) addlo r5, r5, #1 @ next section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Map our RAM from the start to the end of the kernel .bss section.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ldr r6, =(_end - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) orr r3, r8, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 1: str r3, [r0], #1 << PMD_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) add r3, r3, #1 << SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cmp r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bls 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Map the kernel image separately as it is not located in RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mov r3, pc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mov r3, r3, lsr #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) orr r3, r7, r3, lsl #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ldr r6, =(_edata_loc - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) add r0, r0, #1 << PMD_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 1: cmp r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) add r3, r3, #1 << SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) strls r3, [r0], #1 << PMD_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bls 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Then map boot params address in r2 if specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mov r0, r2, lsr #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) cmp r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ldrne r3, =FDT_FIXED_BASE >> (SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) addne r3, r3, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) orrne r6, r7, r0, lsl #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) strne r6, [r3], #1 << PMD_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) addne r6, r6, #1 << SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) strne r6, [r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sub r4, r4, #4 @ Fixup page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) @ for 64-bit descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #ifdef CONFIG_DEBUG_LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Map in IO space for serial debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * This allows debug messages to be output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * via a serial console before paging_init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) addruart r7, r3, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mov r3, r3, lsr #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mov r3, r3, lsl #PMD_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) add r0, r4, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mov r3, r7, lsr #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) orr r3, r7, r3, lsl #SECTION_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mov r7, #1 << (54 - 32) @ XN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #ifdef CONFIG_CPU_ENDIAN_BE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) str r7, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) str r3, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) str r3, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) str r7, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) orr r3, r3, #PMD_SECT_XN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) str r3, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* we don't need any serial debugging mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * If we're using the NetWinder or CATS, we also need to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * in the 16550-type serial port for the debug messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) orr r3, r7, #0x7c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) str r3, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_ARCH_RPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Map in screen at 0x02000000 & SCREEN2_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Similar reasons here - for debug. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * only for Acorn RiscPC architectures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) orr r3, r7, #0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) str r3, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) str r3, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sub r4, r4, #0x1000 @ point to the PGD table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ENDPROC(__create_page_tables)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .ltorg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __turn_mmu_on_loc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .long .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .long __turn_mmu_on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .long __turn_mmu_on_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #if defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ENTRY(secondary_startup_arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) THUMB( badr r9, 1f ) @ Kernel is entered in ARM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) THUMB( .thumb ) @ switch to Thumb now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) THUMB(1: )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ENTRY(secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Common entry point for secondary CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * the processor type - there is no need to check the machine type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * as it has already been validated by the primary processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ARM_BE8(setend be) @ ensure we are in BE8 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef CONFIG_ARM_VIRT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bl __hyp_stub_install_secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) safe_svcmode_maskall r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mrc p15, 0, r9, c0, c0 @ get processor id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) bl __lookup_processor_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) movs r10, r5 @ invalid processor?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) moveq r0, #'p' @ yes, error 'p'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) THUMB( it eq ) @ force fixup-able long branch encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) beq __error_p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Use the page tables supplied from __cpu_up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) adr r4, __secondary_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ldmia r4, {r5, r7, r12} @ address to jump to after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sub lr, r4, r5 @ mmu has been enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) add r3, r7, lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ldrd r4, r5, [r3, #0] @ get secondary_data.pgdir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ARM_BE8(eor r4, r4, r5) @ without using a temp reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ldr r8, [r3, #8] @ get secondary_data.swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) badr lr, __enable_mmu @ return address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mov r13, r12 @ __secondary_switched address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ldr r12, [r10, #PROCINFO_INITFUNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) add r12, r12, r10 @ initialise processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) @ (return control reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ENDPROC(secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ENDPROC(secondary_startup_arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * r6 = &secondary_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ENTRY(__secondary_switched)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ldr sp, [r7, #12] @ get secondary_data.stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mov fp, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) b secondary_start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ENDPROC(__secondary_switched)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .type __secondary_data, %object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __secondary_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .long .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .long secondary_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .long __secondary_switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif /* defined(CONFIG_SMP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Setup common bits before finally enabling the MMU. Essentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * this is just loading the page table pointer and domain access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * registers. All these registers need to be preserved by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * processor setup function (or set in the case of r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * r0 = cp#15 control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * r1 = machine ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * r2 = atags or dtb pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * r4 = TTBR pointer (low word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * r5 = TTBR pointer (high word if LPAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * r9 = processor ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * r13 = *virtual* address to jump to upon completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __enable_mmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) orr r0, r0, #CR_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) bic r0, r0, #CR_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #ifdef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) bic r0, r0, #CR_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #ifdef CONFIG_CPU_BPREDICT_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) bic r0, r0, #CR_Z
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #ifdef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) bic r0, r0, #CR_I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mcrr p15, 0, r4, r5, c2 @ load TTBR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mov r5, #DACR_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mcr p15, 0, r5, c3, c0, 0 @ load domain access register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) b __turn_mmu_on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ENDPROC(__enable_mmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Enable the MMU. This completely changes the structure of the visible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * memory space. You will not be able to trace execution through this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * If you have an enquiry about this, *please* check the linux-arm-kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * mailing list archives BEFORE sending another post to the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * r0 = cp#15 control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * r1 = machine ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * r2 = atags or dtb pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * r9 = processor ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * r13 = *virtual* address to jump to upon completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * other registers depend on the function called upon completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ENTRY(__turn_mmu_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mov r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) instr_sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mcr p15, 0, r0, c1, c0, 0 @ write control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) mrc p15, 0, r3, c0, c0, 0 @ read id reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) instr_sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mov r3, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mov r3, r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __turn_mmu_on_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ENDPROC(__turn_mmu_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #ifdef CONFIG_SMP_ON_UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __fixup_smp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) and r3, r9, #0x000f0000 @ architecture version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) teq r3, #0x000f0000 @ CPU ID supported?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bne __fixup_smp_on_up @ no, assume UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bic r3, r9, #0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) bic r3, r3, #0x0000000f @ mask 0xff00fff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mov r4, #0x41000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) orr r4, r4, #0x0000b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) orr r4, r4, #0x00000020 @ val 0x4100b020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) teq r3, r4 @ ARM 11MPCore?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) reteq lr @ yes, assume SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) and r0, r0, #0xc0000000 @ multiprocessing extensions and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) teq r0, #0x80000000 @ not part of a uniprocessor system?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bne __fixup_smp_on_up @ no, assume UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) @ Core indicates it is SMP. Check for Aegis SOC where a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) @ Cortex-A9 CPU is present but SMP operations fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mov r4, #0x41000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) orr r4, r4, #0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) orr r4, r4, #0x00000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) teq r3, r4 @ Check for ARM Cortex-A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) retne lr @ Not ARM Cortex-A9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) @ below address check will need to be #ifdef'd or equivalent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) @ for the Aegis platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mrc p15, 4, r0, c15, c0 @ get SCU base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) teq r0, #0x0 @ '0' on actual UP A9 hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) beq __fixup_smp_on_up @ So its an A9 UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ldr r0, [r0, #4] @ read SCU Config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ARM_BE8(rev r0, r0) @ byteswap if big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) and r0, r0, #0x3 @ number of CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) teq r0, #0x0 @ is 1?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) retne lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __fixup_smp_on_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) adr r0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ldmia r0, {r3 - r5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) sub r3, r0, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) add r4, r4, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) add r5, r5, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) b __do_fixup_smp_on_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ENDPROC(__fixup_smp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 1: .word .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .word __smpalt_begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .word __smpalt_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .pushsection .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .globl smp_on_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) smp_on_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ALT_SMP(.long 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ALT_UP(.long 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) __do_fixup_smp_on_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cmp r4, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) reths lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ldmia r4!, {r0, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ARM( str r6, [r0, r3] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) THUMB( add r0, r0, r3 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #ifdef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) THUMB( strh r6, [r0] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) b __do_fixup_smp_on_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ENDPROC(__do_fixup_smp_on_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ENTRY(fixup_smp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) stmfd sp!, {r4 - r6, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mov r4, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) add r5, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mov r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bl __do_fixup_smp_on_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ldmfd sp!, {r4 - r6, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ENDPROC(fixup_smp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #ifdef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define LOW_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define HIGH_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define LOW_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define HIGH_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* __fixup_pv_table - patch the stub instructions with the delta between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * can be expressed by an immediate shifter operand. The stub instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * has a form of '(add|sub) rd, rn, #imm'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) __fixup_pv_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) adr r0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ldmia r0, {r3-r7}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mvn ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) add r4, r4, r3 @ adjust table start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) add r5, r5, r3 @ adjust table end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) add r7, r7, r3 @ adjust __pv_offset address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mov r6, r3, lsr #24 @ constant for add/sub instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) teq r3, r6, lsl #24 @ must be 16MiB aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) THUMB( it ne @ cross section branch )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) bne __error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) b __fixup_a_pv_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ENDPROC(__fixup_pv_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 1: .long .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .long __pv_table_begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .long __pv_table_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 2: .long __pv_phys_pfn_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .long __pv_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) __fixup_a_pv_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) adr r0, 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ldr r6, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) add r6, r6, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mov r6, r6, lsr #24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) cmn r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #ifdef CONFIG_THUMB2_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) lsls r6, #24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) beq 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) clz r7, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) lsr r6, #24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) lsl r6, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) bic r6, #0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) lsrs r7, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) orrcs r6, #0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) orr r6, r6, r7, lsl #12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) orr r6, #0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) b 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 1: add r7, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ldrh ip, [r7, #2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ARM_BE8(rev16 ip, ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tst ip, #0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) and ip, #0x8f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) orrne ip, r6 @ mask in offset bits 31-24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) orreq ip, r0 @ mask in offset bits 7-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ARM_BE8(rev16 ip, ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) strh ip, [r7, #2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) bne 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ldrh ip, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ARM_BE8(rev16 ip, ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) bic ip, #0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) orr ip, ip, r0, lsr #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ARM_BE8(rev16 ip, ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) strh ip, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 2: cmp r4, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ldrcc r7, [r4], #4 @ use branch for delay slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) bcc 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) bx lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) b 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 1: ldr ip, [r7, r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #ifdef CONFIG_CPU_ENDIAN_BE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) @ in BE8, we load data in BE, but instructions still in LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bic ip, ip, #0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tst ip, #0x000f0000 @ check the rotation field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) biceq ip, ip, #0x00004000 @ clear bit 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) bic ip, ip, #0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tst ip, #0xf00 @ check the rotation field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) orrne ip, ip, r6 @ mask in offset bits 31-24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) biceq ip, ip, #0x400000 @ clear bit 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) orreq ip, ip, r0 @ mask in offset bits 7-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) str ip, [r7, r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 2: cmp r4, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ldrcc r7, [r4], #4 @ use branch for delay slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) bcc 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ENDPROC(__fixup_a_pv_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 3: .long __pv_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ENTRY(fixup_pv_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) stmfd sp!, {r4 - r7, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mov r3, #0 @ no offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mov r4, r0 @ r0 = table start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) add r5, r0, r1 @ r1 = table size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) bl __fixup_a_pv_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ldmfd sp!, {r4 - r7, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ENDPROC(fixup_pv_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .globl __pv_phys_pfn_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .type __pv_phys_pfn_offset, %object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) __pv_phys_pfn_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .globl __pv_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .type __pv_offset, %object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) __pv_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .quad 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .size __pv_offset, . -__pv_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #include "head-common.S"
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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