Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *  linux/arch/arm/kernel/fiqasm.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *  Derived from code originally in linux/arch/arm/kernel/fiq.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Copyright (C) 1998 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Copyright (C) 1998, 1999 Phil Blundell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *  Copyright (C) 2011, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *  FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *  FIQ support re-written by Russell King to be more generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *  v7/Thumb-2 compatibility modifications by Linaro Limited, 2011.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * Taking an interrupt in FIQ mode is death, so both these functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * disable irqs for the duration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ENTRY(__set_fiq_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	mov	r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	mrs	r1, cpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	msr	cpsr_c, r2	@ select FIQ mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	mov	r0, r0		@ avoid hazard prior to ARMv4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	ldmia	r0!, {r8 - r12}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	ldr	sp, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	ldr	lr, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	msr	cpsr_c, r1	@ return to SVC mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	mov	r0, r0		@ avoid hazard prior to ARMv4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ENDPROC(__set_fiq_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ENTRY(__get_fiq_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	mov	r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	mrs	r1, cpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	msr	cpsr_c, r2	@ select FIQ mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	mov	r0, r0		@ avoid hazard prior to ARMv4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	stmia	r0!, {r8 - r12}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	str	sp, [r0], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	str	lr, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	msr	cpsr_c, r1	@ return to SVC mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	mov	r0, r0		@ avoid hazard prior to ARMv4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ENDPROC(__get_fiq_regs)