Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/kernel/dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 1995-2000 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Front-end to the DMA handling.  This handles the allocation/freeing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  of DMA channels, and provides a unified interface to the machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  DMA facilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) DEFINE_RAW_SPINLOCK(dma_spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) EXPORT_SYMBOL(dma_spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static dma_t *dma_chan[MAX_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static inline dma_t *dma_channel(unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	if (chan >= MAX_DMA_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return dma_chan[chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) int __init isa_dma_add(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (!dma->d_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	sg_init_table(&dma->buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (dma_chan[chan])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	dma_chan[chan] = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Request DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * On certain platforms, we have to allocate an interrupt as well...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) int request_dma(unsigned int chan, const char *device_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (!dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		goto bad_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (xchg(&dma->lock, 1) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		goto busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	dma->device_id = device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	dma->active    = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	dma->invalid   = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (dma->d_ops->request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		ret = dma->d_ops->request(chan, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		xchg(&dma->lock, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) bad_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	pr_err("dma: trying to allocate DMA%d\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) busy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) EXPORT_SYMBOL(request_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * Free DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * On certain platforms, we have to free interrupt as well...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) void free_dma(unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (!dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		goto bad_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (dma->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		pr_err("dma%d: freeing active DMA\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		dma->d_ops->disable(chan, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		dma->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (xchg(&dma->lock, 0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (dma->d_ops->free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			dma->d_ops->free(chan, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	pr_err("dma%d: trying to free free DMA\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bad_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	pr_err("dma: trying to free DMA%d\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXPORT_SYMBOL(free_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Set DMA Scatter-Gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void set_dma_sg (unsigned int chan, struct scatterlist *sg, int nr_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (dma->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		pr_err("dma%d: altering DMA SG while DMA active\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	dma->sg = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	dma->sgcount = nr_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	dma->invalid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EXPORT_SYMBOL(set_dma_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Set DMA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * Copy address to the structure, and set the invalid bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __set_dma_addr (unsigned int chan, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (dma->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		pr_err("dma%d: altering DMA address while DMA active\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	dma->sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	dma->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dma->invalid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXPORT_SYMBOL(__set_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Set DMA byte count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * Copy address to the structure, and set the invalid bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void set_dma_count (unsigned int chan, unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (dma->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		pr_err("dma%d: altering DMA count while DMA active\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	dma->sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	dma->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	dma->invalid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EXPORT_SYMBOL(set_dma_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Set DMA direction mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void set_dma_mode (unsigned int chan, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (dma->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		pr_err("dma%d: altering DMA mode while DMA active\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	dma->dma_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	dma->invalid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) EXPORT_SYMBOL(set_dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Enable DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void enable_dma (unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (!dma->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		goto free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (dma->active == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dma->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		dma->d_ops->enable(chan, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	pr_err("dma%d: trying to enable free DMA\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EXPORT_SYMBOL(enable_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Disable DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void disable_dma (unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (!dma->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		goto free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (dma->active == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		dma->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dma->d_ops->disable(chan, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	pr_err("dma%d: trying to disable free DMA\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) EXPORT_SYMBOL(disable_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * Is the specified DMA channel active?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int dma_channel_active(unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return dma->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) EXPORT_SYMBOL(dma_channel_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void set_dma_page(unsigned int chan, char pagenr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	pr_err("dma%d: trying to set_dma_page\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) EXPORT_SYMBOL(set_dma_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void set_dma_speed(unsigned int chan, int cycle_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (dma->d_ops->setspeed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		ret = dma->d_ops->setspeed(chan, dma, cycle_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	dma->speed = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EXPORT_SYMBOL(set_dma_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int get_dma_residue(unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dma_t *dma = dma_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (dma->d_ops->residue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		ret = dma->d_ops->residue(chan, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXPORT_SYMBOL(get_dma_residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int proc_dma_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	for (i = 0 ; i < MAX_DMA_CHANNELS ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		dma_t *dma = dma_channel(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (dma && dma->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			seq_printf(m, "%2d: %s\n", i, dma->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int __init proc_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	proc_create_single("dma", 0, NULL, proc_dma_show);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __initcall(proc_dma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif