^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/kernel/dma-isa.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999-2000 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ISA DMA primitives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Taken from various sources, including:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * linux/include/asm/dma.h: Defines for using and allocating dma channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Written by Hennus Bergman, 1992.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * High DMA channel support & info by Hannu Savolainen and John Boyd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Nov. 1992.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * arch/arm/kernel/dma-ebsa285.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1998 Phil Blundell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ISA_DMA_MASK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ISA_DMA_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ISA_DMA_CLRFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ISA_DMA_PGHI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ISA_DMA_PGLO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISA_DMA_ADDR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ISA_DMA_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static unsigned int isa_dma_port[8][7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* MASK MODE CLRFF PAGE_HI PAGE_LO ADDR COUNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int isa_get_dma_residue(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) count = 1 + inb(io_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) count |= inb(io_port) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return chan < 4 ? count : (count << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct device isa_dma_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .init_name = "fallback device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .coherent_dma_mask = ~(dma_addr_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .dma_mask = &isa_dma_dev.coherent_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void isa_enable_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (dma->invalid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long address, length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) enum dma_data_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mode = (chan & 3) | dma->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (dma->dma_mode & DMA_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case DMA_MODE_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) direction = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case DMA_MODE_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case DMA_MODE_CASCADE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) direction = DMA_BIDIRECTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) direction = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!dma->sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Cope with ISA-style drivers which expect cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * coherence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dma->sg = &dma->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dma->sgcount = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dma->buf.length = dma->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dma->buf.dma_address = dma_map_single(&isa_dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dma->addr, dma->count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) address = dma->buf.dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) length = dma->buf.length - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (chan >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) address >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) length >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) outb(address, isa_dma_port[chan][ISA_DMA_ADDR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) outb(length, isa_dma_port[chan][ISA_DMA_COUNT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) outb(mode, isa_dma_port[chan][ISA_DMA_MODE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dma->invalid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void isa_disable_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct dma_ops isa_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .type = "ISA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .enable = isa_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .disable = isa_disable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .residue = isa_get_dma_residue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct resource dma_resources[] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "dma1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .start = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .end = 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "dma low page",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .start = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .end = 0x008f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "dma2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .start = 0x00c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .end = 0x00df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "dma high page",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .start = 0x0480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .end = 0x048f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static dma_t isa_dma[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * ISA DMA always starts at channel 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void __init isa_init_dma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Try to autodetect presence of an ISA DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * We do some minimal initialisation, and check that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * channel 0's DMA address registers are writeable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) outb(0xff, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) outb(0xff, 0xda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Write high and low address, and then read them back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * in the same order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) outb(0x55, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) outb(0xaa, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (inb(0) == 0x55 && inb(0) == 0xaa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int chan, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (chan = 0; chan < 8; chan++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) isa_dma[chan].d_ops = &isa_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) isa_disable_dma(chan, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) outb(0x40, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) outb(0x41, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) outb(0x42, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) outb(0x43, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) outb(0xc0, 0xd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) outb(0x41, 0xd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) outb(0x42, 0xd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) outb(0x43, 0xd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) outb(0, 0xd4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) outb(0x10, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) outb(0x10, 0xd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Is this correct? According to my documentation, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * doesn't appear to be. It should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * outb(0x3f, 0x40b); outb(0x3f, 0x4d6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) outb(0x30, 0x40b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) outb(0x31, 0x40b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) outb(0x32, 0x40b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) outb(0x33, 0x40b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) outb(0x31, 0x4d6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) outb(0x32, 0x4d6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) outb(0x33, 0x4d6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) for (i = 0; i < ARRAY_SIZE(dma_resources); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) request_resource(&ioport_resource, dma_resources + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (chan = 0; chan < 8; chan++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ret = isa_dma_add(chan, &isa_dma[chan]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pr_err("ISADMA%u: unable to register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) chan, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) request_dma(DMA_ISA_CASCADE, "cascade");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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