Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/kernel/devtree.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) extern struct of_cpu_method __cpu_method_of_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const struct of_cpu_method __cpu_method_of_table_sentinel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	__used __section("__cpu_method_of_table_end");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static int __init set_smp_ops_by_method(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	const char *method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct of_cpu_method *m = __cpu_method_of_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (of_property_read_string(node, "enable-method", &method))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	for (; m->method; m++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		if (!strcmp(m->method, method)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			smp_set_ops(m->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static inline int set_smp_ops_by_method(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * and builds the cpu logical map array containing MPIDR values related to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * logical cpus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * Updates the cpu possible mask with the number of parsed cpu nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) void __init arm_dt_init_cpu_maps(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * Temp logical map is initialized with UINT_MAX values that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * considered invalid logical map entries since the logical map must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * read as 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct device_node *cpu, *cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int found_method = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 i, j, cpuidx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	bool bootcpu_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	cpus = of_find_node_by_path("/cpus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (!cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	for_each_of_cpu_node(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		const __be32 *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		int prop_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		u32 hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		pr_debug(" * %pOF...\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 * A device tree containing CPU nodes with missing "reg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * properties is considered invalid to build the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 * cpu_logical_map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		cell = of_get_property(cpu, "reg", &prop_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (!cell || prop_bytes < sizeof(*cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			pr_debug(" * %pOF missing reg property\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			of_node_put(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		 * Bits n:24 must be set to 0 in the DT since the reg property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 * defines the MPIDR[23:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			hwid = be32_to_cpu(*cell++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			prop_bytes -= sizeof(*cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		} while (!hwid && prop_bytes > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		if (prop_bytes || (hwid & ~MPIDR_HWID_BITMASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			of_node_put(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		 * Duplicate MPIDRs are a recipe for disaster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		 * Scan all initialized entries and check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		 * duplicates. If any is found just bail out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		 * temp values were initialized to UINT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		 * to avoid matching valid MPIDR[23:0] values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		for (j = 0; j < cpuidx; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			if (WARN(tmp_map[j] == hwid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				 "Duplicate /cpu reg properties in the DT\n")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				of_node_put(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		 * Build a stashed array of MPIDR values. Numbering scheme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		 * requires that if detected the boot CPU must be assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		 * logical id 0. Other CPUs get sequential indexes starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		 * from 1. If a CPU node with a reg property matching the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		 * boot CPU MPIDR is detected, this is recorded so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		 * logical map built from DT is validated and can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		 * to override the map created in smp_setup_processor_id().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (hwid == mpidr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			bootcpu_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			i = cpuidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 					       "max cores %u, capping them\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					       cpuidx, nr_cpu_ids)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			cpuidx = nr_cpu_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			of_node_put(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		tmp_map[i] = hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		if (!found_method)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			found_method = set_smp_ops_by_method(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * Fallback to an enable-method in the cpus node if nothing found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * a cpu node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!found_method)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		set_smp_ops_by_method(cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!bootcpu_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * Since the boot CPU node contains proper data, and all nodes have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * a reg property, the DT CPU list can be considered valid and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * logical map created in smp_setup_processor_id() can be overridden
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	for (i = 0; i < cpuidx; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		set_cpu_possible(i, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		cpu_logical_map(i) = tmp_map[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return phys_id == cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const void * __init arch_get_next_mach(const char *const **match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	static const struct machine_desc *mdesc = __arch_info_begin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	const struct machine_desc *m = mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (m >= __arch_info_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	mdesc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	*match = m->dt_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * setup_machine_fdt - Machine setup when an dtb was passed to the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * @dt_virt: virtual address of dt blob
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * If a dtb was passed to the kernel in r2, then use it to choose the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * correct machine_desc and to setup the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct machine_desc * __init setup_machine_fdt(void *dt_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	const struct machine_desc *mdesc, *mdesc_best = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #if defined(CONFIG_ARCH_MULTIPLATFORM) || defined(CONFIG_ARM_SINGLE_ARMV7M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	DT_MACHINE_START(GENERIC_DT, "Generic DT based system")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.l2c_aux_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.l2c_aux_mask = ~0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mdesc_best = &__mach_desc_GENERIC_DT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (!dt_virt || !early_init_dt_verify(dt_virt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	mdesc = of_flat_dt_match_machine(mdesc_best, arch_get_next_mach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (!mdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		const char *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		unsigned long dt_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		early_print("\nError: unrecognized/unsupported "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			    "device tree compatible list:\n[ ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		dt_root = of_get_flat_dt_root();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		prop = of_get_flat_dt_prop(dt_root, "compatible", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			early_print("'%s' ", prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			size -= strlen(prop) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			prop += strlen(prop) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		early_print("]\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		dump_machine_table(); /* does not return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* We really don't want to do this, but sometimes firmware provides buggy data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (mdesc->dt_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		mdesc->dt_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	early_init_dt_scan_nodes();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Change machine number to match the mdesc we're using */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	__machine_arch_type = mdesc->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }