^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1995-2003 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * 2001-2002 Keith Owens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Generate definitions needed by assembly language modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This code generates raw asm output which is post-processed to extract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and format the required data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/kexec-internal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/glue-df.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/glue-pf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/procinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/vdso_datapage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kbuild.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "signal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Make sure that the compiler and target are compatible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #if defined(__APCS_26__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int main(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifdef CONFIG_STACKPROTECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE(TI_TASK, offsetof(struct thread_info, task));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_VFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_ARM_THUMBEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_IWMMXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_CRUNCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE(TI_CRUNCH_STATE, offsetof(struct thread_info, crunchstate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifdef CONFIG_STACKPROTECTOR_PER_TASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE(TI_STACK_CANARY, offsetof(struct thread_info, stack_canary));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEFINE(THREAD_SZ_ORDER, THREAD_SIZE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEFINE(S_R2, offsetof(struct pt_regs, ARM_r2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE(S_R3, offsetof(struct pt_regs, ARM_r3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE(S_R4, offsetof(struct pt_regs, ARM_r4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE(S_R5, offsetof(struct pt_regs, ARM_r5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEFINE(S_R6, offsetof(struct pt_regs, ARM_r6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEFINE(S_R7, offsetof(struct pt_regs, ARM_r7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEFINE(S_R8, offsetof(struct pt_regs, ARM_r8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFINE(S_R9, offsetof(struct pt_regs, ARM_r9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEFINE(S_R10, offsetof(struct pt_regs, ARM_r10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEFINE(S_FP, offsetof(struct pt_regs, ARM_fp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEFINE(S_IP, offsetof(struct pt_regs, ARM_ip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEFINE(S_SP, offsetof(struct pt_regs, ARM_sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEFINE(S_LR, offsetof(struct pt_regs, ARM_lr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEFINE(S_PC, offsetof(struct pt_regs, ARM_pc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEFINE(S_PSR, offsetof(struct pt_regs, ARM_cpsr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEFINE(SVC_DACR, offsetof(struct svc_pt_regs, dacr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEFINE(SVC_ADDR_LIMIT, offsetof(struct svc_pt_regs, addr_limit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEFINE(SVC_REGS_SIZE, sizeof(struct svc_pt_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DEFINE(SIGFRAME_RC3_OFFSET, offsetof(struct sigframe, retcode[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DEFINE(RT_SIGFRAME_RC3_OFFSET, offsetof(struct rt_sigframe, sig.retcode[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_CPU_HAS_ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEFINE(VM_EXEC, VM_EXEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEFINE(PAGE_SZ, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEFINE(SYS_ERROR0, 0x9f0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef MULTI_DABORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef MULTI_PABORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef MULTI_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEFINE(CPU_SLEEP_SIZE, offsetof(struct processor, suspend_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEFINE(CPU_DO_SUSPEND, offsetof(struct processor, do_suspend));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEFINE(CPU_DO_RESUME, offsetof(struct processor, do_resume));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef MULTI_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_VDSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE(VDSO_DATA_SIZE, sizeof(union vdso_data_store));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifdef CONFIG_ARM_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEFINE(MPU_RNG_INFO_RNGS, offsetof(struct mpu_rgn_info, rgns));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEFINE(MPU_RNG_INFO_USED, offsetof(struct mpu_rgn_info, used));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEFINE(MPU_RNG_SIZE, sizeof(struct mpu_rgn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE(MPU_RGN_DRBAR, offsetof(struct mpu_rgn, drbar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE(MPU_RGN_DRSR, offsetof(struct mpu_rgn, drsr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE(MPU_RGN_DRACR, offsetof(struct mpu_rgn, dracr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEFINE(MPU_RGN_PRBAR, offsetof(struct mpu_rgn, prbar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE(MPU_RGN_PRLAR, offsetof(struct mpu_rgn, prlar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE(KEXEC_START_ADDR, offsetof(struct kexec_relocate_data, kexec_start_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE(KEXEC_INDIR_PAGE, offsetof(struct kexec_relocate_data, kexec_indirection_page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEFINE(KEXEC_MACH_TYPE, offsetof(struct kexec_relocate_data, kexec_mach_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE(KEXEC_R2, offsetof(struct kexec_relocate_data, kexec_r2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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