Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Debugging macro include header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2011 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define UART_CR_OFFSET		0x00  /* Control Register [8:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define UART_SR_OFFSET		0x2C  /* Channel Status [11:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define UART_FIFO_OFFSET	0x30  /* FIFO [15:0] or [7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define UART_SR_TXFULL		0x00000010	/* TX FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UART0_PHYS		0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UART0_VIRT		0xF0800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define UART1_PHYS		0xE0001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UART1_VIRT		0xF0801000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) # define LL_UART_PADDR		UART1_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define LL_UART_VADDR		UART1_VIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) # define LL_UART_PADDR		UART0_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define LL_UART_VADDR		UART0_VIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		ldr	\rp, =LL_UART_PADDR	@ physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		ldr	\rv, =LL_UART_VADDR	@ virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		.macro	senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		strb	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 1001:		ldr	\rd, [\rx, #UART_SR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ARM_BE8(	rev	\rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		tst	\rd, #UART_SR_TXEMPTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.macro	busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 1002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ARM_BE8(	rev	\rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		tst	\rd, #UART_SR_TXFULL		@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		bne	1002b			@ wait if FIFO is full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		.endm