Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define VF_UART0_BASE_ADDR	0x40027000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define VF_UART1_BASE_ADDR	0x40028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define VF_UART2_BASE_ADDR	0x40029000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define VF_UART3_BASE_ADDR	0x4002a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define VF_UART_BASE_ADDR(n)	VF_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VF_UART_BASE(n)		VF_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VF_UART_PHYSICAL_BASE	VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VF_UART_VIRTUAL_BASE	0xfe000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	ldr	\rp, =VF_UART_PHYSICAL_BASE 	@ physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	and	\rv, \rp, #0xffffff		@ offset within 16MB section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	add	\rv, \rv, #VF_UART_VIRTUAL_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.macro	senduart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	strb	\rd, [\rx, #0x7]	@ Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	.macro	busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 1001:	ldrb	\rd, [\rx, #0x4]	@ Status Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	tst	\rd, #1 << 6		@ TC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	beq	1001b			@ wait until transmit done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	.endm