Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* arch/arm/mach-realview/include/mach/debug-macro.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Debugging macro include header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Copyright (C) 1994-1999 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DEBUG_LL_PHYS_BASE		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DEBUG_LL_UART_OFFSET		0x00009000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DEBUG_LL_PHYS_BASE_RS1		0x1c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DEBUG_LL_UART_OFFSET_RS1	0x00090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEBUG_LL_UART_PHYS_CRX		0xb0090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEBUG_LL_VIRT_BASE		0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		.macro	addruart,rp,rv,tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		.arch   armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		@ Make an educated guess regarding the memory map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		@ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		@   should use UART at 0x10009000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		@ - all other (RS1 complaint) tiles use UART mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		@   at 0x1c090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		mrc	p15, 0, \rp, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		movw	\rv, #0xc091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		movt	\rv, #0x410f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		cmp	\rp, \rv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		@ Original memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		moveq	\rp, #DEBUG_LL_UART_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		orreq	\rv, \rp, #DEBUG_LL_VIRT_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		orreq	\rp, \rp, #DEBUG_LL_PHYS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		@ RS1 memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		movne	\rp, #DEBUG_LL_UART_OFFSET_RS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		orrne	\rv, \rp, #DEBUG_LL_VIRT_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		orrne	\rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <debug/pl01x.S>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif