Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Debugging macro include header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2009 ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #if CONFIG_UX500_DEBUG_UART > 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #error Invalid Ux500 debug UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * DEBUG_LL only works if only one SOC is built in.  We don't use #else below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * in order to get "__UX500_UART redefined" warnings if more than one SOC is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * built, so that there's some hint during the build that something is wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_UX500_SOC_DB8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define U8500_UART0_PHYS_BASE	(0x80120000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define U8500_UART1_PHYS_BASE	(0x80121000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define U8500_UART2_PHYS_BASE	(0x80007000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define __UX500_PHYS_UART(n)	U8500_UART##n##_PHYS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #if !defined(__UX500_PHYS_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #error Unknown SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UX500_PHYS_UART(n)	__UX500_PHYS_UART(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UART_PHYS_BASE	UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UART_VIRT_BASE	(0xfff07000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ldr	\rp, =UART_PHYS_BASE		@ no, physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	ldr	\rv, =UART_VIRT_BASE		@ yes, virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <debug/pl01x.S>