Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2010,2011 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Colin Cross <ccross@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Erik Gilling <konkers@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	Doug Anderson <dianders@chromium.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Portions based on mach-omap2's debug-macro.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 1994-1999 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define UART_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* Physical addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TEGRA_CLK_RESET_BASE		0x60006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TEGRA_APB_MISC_BASE		0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TEGRA_UARTA_BASE		0x70006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TEGRA_UARTB_BASE		0x70006040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TEGRA_UARTC_BASE		0x70006200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEGRA_UARTD_BASE		0x70006300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TEGRA_UARTE_BASE		0x70006400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TEGRA_PMC_BASE			0x7000e400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TEGRA_CLK_RST_DEVICES_L		(TEGRA_CLK_RESET_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TEGRA_CLK_RST_DEVICES_H		(TEGRA_CLK_RESET_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA_CLK_RST_DEVICES_U		(TEGRA_CLK_RESET_BASE + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TEGRA_CLK_OUT_ENB_L		(TEGRA_CLK_RESET_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TEGRA_CLK_OUT_ENB_H		(TEGRA_CLK_RESET_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA_CLK_OUT_ENB_U		(TEGRA_CLK_RESET_BASE + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TEGRA_PMC_SCRATCH20		(TEGRA_PMC_BASE + 0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TEGRA_APB_MISC_GP_HIDREV	(TEGRA_APB_MISC_BASE + 0x804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * Must be section-aligned since a section mapping is used early on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define UART_VIRTUAL_BASE		0xfe800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define checkuart(rp, rv, lhu, bit, uart) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		/* Load address of CLK_RST register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		ldr	rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		/* Load value from CLK_RST register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		ldr	rp, [rp, #0] ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		/* Test UART's reset bit */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		tst	rp, #(1 << bit) ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		/* If set, can't use UART; jump to save no UART */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		bne	90f ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		/* Load address of CLK_OUT_ENB register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		ldr	rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		/* Load value from CLK_OUT_ENB register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		ldr	rp, [rp, #0] ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		/* Test UART's clock enable bit */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		tst	rp, #(1 << bit) ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		/* If clear, can't use UART; jump to save no UART */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		beq	90f ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		/* Passed all tests, load address of UART registers */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		ldr	rp, =TEGRA_UART##uart##_BASE ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		/* Jump to save UART address */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		b 91f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.macro  addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		adr	\rp, 99f		@ actual addr of 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		ldr	\rv, [\rp]		@ linked addr is stored there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		sub	\rv, \rv, \rp		@ offset between the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		ldr	\rp, [\rp, #4]		@ linked tegra_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		sub	\tmp, \rp, \rv		@ actual tegra_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		ldr	\rp, [\tmp]		@ Load tegra_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		cmp	\rp, #1			@ needs initialization?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		bne	100f			@ no; go load the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		mov	\rv, #0			@ yes; record init is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		str	\rv, [\tmp]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		/* Check ODMDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 10:		ldr	\rp, =TEGRA_PMC_SCRATCH20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		ldr	\rp, [\rp, #0]		@ Load PMC_SCRATCH20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		lsr	\rv, \rp, #18		@ 19:18 are console type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		and	\rv, \rv, #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		cmp	\rv, #2			@ 2 and 3 mean DCC, UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		beq	11f			@ some boards swap the meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		cmp	\rv, #3			@ so accept either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		bne	90f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 11:		lsr	\rv, \rp, #15		@ 17:15 are UART ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		and	\rv, #7	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		cmp	\rv, #0			@ UART 0?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		beq	20f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		cmp	\rv, #1			@ UART 1?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		beq	21f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		cmp	\rv, #2			@ UART 2?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		beq	22f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		cmp	\rv, #3			@ UART 3?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		beq	23f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		cmp	\rv, #4			@ UART 4?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		beq	24f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		b	90f			@ invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)     defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		/* Check UART A validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 20:		checkuart(\rp, \rv, L, 6, A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)     defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		/* Check UART B validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 21:		checkuart(\rp, \rv, L, 7, B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)     defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		/* Check UART C validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 22:		checkuart(\rp, \rv, H, 23, C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)     defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/* Check UART D validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 23:		checkuart(\rp, \rv, U, 1, D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)     defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		/* Check UART E validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		checkuart(\rp, \rv, U, 2, E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* No valid UART found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 90:		mov	\rp, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		/* fall through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		/* Record whichever UART we chose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 91:		str	\rp, [\tmp, #4]		@ Store in tegra_uart_phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		cmp	\rp, #0			@ Valid UART address?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		bne	92f			@ Yes, go process it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		str	\rp, [\tmp, #8]		@ Store 0 in tegra_uart_virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		b	100f			@ Done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 92:		and	\rv, \rp, #0xffffff	@ offset within 1MB section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		add	\rv, \rv, #UART_VIRTUAL_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		str	\rv, [\tmp, #8]		@ Store in tegra_uart_virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		b	100f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 99:		.word	.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #if defined(ZIMAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.word	. + 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * Storage for the state maintained by the macro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * That's because this header is included from multiple files, and we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * want a single copy of the data. In particular, the UART probing code above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * assumes it's running using physical addresses. This is true when this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * is included from head.o, but not when included from debug.o. So we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * to share the probe results between the two copies, rather than having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * to re-run the probing again later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * In the decompressor, we put the storage right here, since common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * isn't included in the decompressor build. This storage data gets put in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * .text even though it's really data, since .data is discarded from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * decompressor. Luckily, .text is writeable in the decompressor, unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		/* Debug UART initialization required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.word	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		/* Debug UART physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		/* Debug UART virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.word	tegra_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.ltorg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		/* Load previously selected UART address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 100:		ldr	\rp, [\tmp, #4]		@ Load tegra_uart_phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		ldr	\rv, [\tmp, #8]		@ Load tegra_uart_virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * check to make sure that the UART address is actually valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.macro	senduart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		cmp	\rx, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		strbne	\rd, [\rx, #UART_TX << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.macro	busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		cmp	\rx, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		beq	1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 1001:		ldrb	\rd, [\rx, #UART_LSR << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		and	\rd, \rd, #UART_LSR_THRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		teq	\rd, #UART_LSR_THRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		bne	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 1002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.macro	waituartcts, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		cmp	\rx, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		beq	1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 1001:		ldrb	\rd, [\rx, #UART_MSR << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		tst	\rd, #UART_MSR_CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 1002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.endm