Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) STMicroelectronics SA 2017 - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author:   Gerald Baeza <gerald.baeza@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifdef CONFIG_STM32F4_DEBUG_UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define STM32_USART_SR_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define STM32_USART_TDR_OFF		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #if defined(CONFIG_STM32F7_DEBUG_UART) || defined(CONFIG_STM32H7_DEBUG_UART) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	defined(CONFIG_STM32MP1_DEBUG_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STM32_USART_SR_OFF		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STM32_USART_TDR_OFF		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STM32_USART_TC			(1 << 6)	/* Tx complete       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STM32_USART_TXE			(1 << 7)	/* Tx data reg empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	ldr	\rp, =CONFIG_DEBUG_UART_PHYS @ physical base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	ldr	\rv, =CONFIG_DEBUG_UART_VIRT @ virt base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .macro  senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	strb    \rd, [\rx, #STM32_USART_TDR_OFF]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .macro  waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 1001:	ldr	\rd, [\rx, #(STM32_USART_SR_OFF)]	@ Read Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	tst	\rd, #STM32_USART_TXE			@ TXE = 1 = tx empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .macro  busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 1001:	ldr	\rd, [\rx, #(STM32_USART_SR_OFF)]	@ Read Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	tst	\rd, #STM32_USART_TC			@ TC = 1 = tx complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .endm