Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-prima2/include/mach/debug-macro.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define SIRF_LLUART_TXFIFO_STATUS	0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define SIRF_LLUART_TXFIFO_DATA	0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SIRF_LLUART_TXFIFO_FULL                       (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef CONFIG_DEBUG_SIRFATLAS7_UART0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SIRF_LLUART_TXFIFO_EMPTY			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SIRF_LLUART_TXFIFO_EMPTY			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	ldr	\rp, =CONFIG_DEBUG_UART_PHYS		@ physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	ldr	\rv, =CONFIG_DEBUG_UART_VIRT		@ virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	.macro	senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	str	\rd, [\rx, #SIRF_LLUART_TXFIFO_DATA]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.macro	busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 1001:	ldr	\rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	tst	\rd, #SIRF_LLUART_TXFIFO_EMPTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)