^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2005, 2007 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* The S5PV210/S5PC110 implementations are as belows. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .macro fifo_level_s5pv210 rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ldr \rd, [\rx, # S3C2410_UFSTAT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) and \rd, \rd, #S5PV210_UFSTAT_TXMASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .macro fifo_full_s5pv210 rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ldr \rd, [\rx, # S3C2410_UFSTAT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) tst \rd, #S5PV210_UFSTAT_TXFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* The S3C2440 implementations are used by default as they are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * most widely re-used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .macro fifo_level_s3c2440 rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ldr \rd, [\rx, # S3C2410_UFSTAT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) and \rd, \rd, #S3C2440_UFSTAT_TXMASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef fifo_level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define fifo_level fifo_level_s3c2440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .macro fifo_full_s3c2440 rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ldr \rd, [\rx, # S3C2410_UFSTAT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) tst \rd, #S3C2440_UFSTAT_TXFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifndef fifo_full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define fifo_full fifo_full_s3c2440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .macro senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) strb \rd, [\rx, # S3C2410_UTXH]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .macro busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ldr \rd, [\rx, # S3C2410_UFCON]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) beq 1001f @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) @ FIFO enabled...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 1003:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) fifo_full \rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bne 1003b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) b 1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) @ busy waiting for non fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ldr \rd, [\rx, # S3C2410_UTRSTAT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tst \rd, #S3C2410_UTRSTAT_TXFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) beq 1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 1002: @ exit busyuart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .macro waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .macro waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ldr \rd, [\rx, # S3C2410_UFCON]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) beq 1001f @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) @ FIFO enabled...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 1003:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) fifo_level \rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) teq \rd, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bne 1003b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) b 1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) @ idle waiting for non fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ldr \rd, [\rx, # S3C2410_UTRSTAT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tst \rd, #S3C2410_UTRSTAT_TXFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) beq 1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 1002: @ exit busyuart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .endm
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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