Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* arch/arm/include/debug/sa1100.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Debugging macro include header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Copyright (C) 1994-1999 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define UTCR3		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define UTDR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define UTSR1		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define UTCR3_TXE	0x00000002	/* Transmit Enable                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		mrc	p15, 0, \rp, c1, c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		tst	\rp, #1			@ MMU enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		moveq	\rp, #0x80000000	@ physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		movne	\rp, #0xf8000000	@ virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		@ We probe for the active serial port here, coherently with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		@ We assume r1 can be clobbered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		@ see if Ser3 is active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		add	\rp, \rp, #0x00050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		ldr	\rv, [\rp, #UTCR3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		tst	\rv, #UTCR3_TXE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		@ if Ser3 is inactive, then try Ser1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		addeq	\rp, \rp, #(0x00010000 - 0x00050000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		ldreq	\rv, [\rp, #UTCR3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		tsteq	\rv, #UTCR3_TXE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		@ if Ser1 is inactive, then try Ser2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		addeq	\rp, \rp, #(0x00030000 - 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		ldreq	\rv, [\rp, #UTCR3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		tsteq	\rv, #UTCR3_TXE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		@ clear top bits, and generate both phys and virt addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		lsl	\rp, \rp, #8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		lsr	\rp, \rp, #8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		orr	\rv, \rp, #0xf8000000	@ virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		orr	\rp, \rp, #0x80000000	@ physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		.macro	senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		str	\rd, [\rx, #UTDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 1001:		ldr	\rd, [\rx, #UTSR1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		tst	\rd, #UTSR1_TNF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		.macro	busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 1001:		ldr	\rd, [\rx, #UTSR1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		tst	\rd, #UTSR1_TBY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		bne	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		.endm