Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas SCIF(A) debugging macro include header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Based on r8a7790.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2012-2013 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 1994-1999 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SCIF_PHYS	CONFIG_DEBUG_UART_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SCIF_VIRT	((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* RZ/A2 SCIFA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FTDR		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FSR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* SCIFA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FTDR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FSR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* SCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FTDR		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FSR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TDFE	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEND	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	ldr	\rp, =SCIF_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	ldr	\rv, =SCIF_VIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	.macro	waituarttxrdy, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 1001:	ldrh	\rd, [\rx, #FSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	tst	\rd, #TDFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.macro	senduart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	strb	\rd, [\rx, #FTDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	ldrh	\rd, [\rx, #FSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	bic	\rd, \rd, #TEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	strh	\rd, [\rx, #FSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.macro	busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 1001:	ldrh	\rd, [\rx, #FSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	tst	\rd, #TEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.endm