Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2007 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Brian Swetland <swetland@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	ldr	\rp, =CONFIG_DEBUG_UART_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	ldr	\rv, =CONFIG_DEBUG_UART_VIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	.macro	senduart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ARM_BE8(rev	\rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	@ Write the 1 character to UARTDM_TF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	str	\rd, [\rx, #0x70]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.macro	waituarttxrdy, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	@ check for TX_EMT in UARTDM_SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	ldr	\rd, [\rx, #0x08]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ARM_BE8(rev     \rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	tst	\rd, #0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	bne	1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	@ wait for TXREADY in UARTDM_ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 1001:	ldr	\rd, [\rx, #0x14]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ARM_BE8(rev     \rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	tst	\rd, #0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	beq 	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 1002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	@ Clear TX_READY by writing to the UARTDM_CR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	mov	\rd, #0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ARM_BE8(rev     \rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	str	\rd, [\rx, #0x10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	@ Write 0x1 to NCF register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	mov 	\rd, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ARM_BE8(rev     \rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	str	\rd, [\rx, #0x40]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	@ UARTDM reg. Read to induce delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	ldr	\rd, [\rx, #0x08]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.macro	busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.endm