Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* arch/arm/mach-imx/include/mach/debug-macro.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Debugging macro include header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Copyright (C) 1994-1999 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "imx-uart.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * stay sync with that.  It's hard to maintain, and should be fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * globally for multi-platform build to use a fixed virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * for low-level debug uart port across platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX_IO_P2V(x)	(						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			(((x) & 0x80000000) >> 7) |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			(0xf4000000 +					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			(((x) & 0x50000000) >> 6) +			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			(((x) & 0x0b000000) >> 4) +			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			(((x) & 0x000fffff))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UART_VADDR	IMX_IO_P2V(UART_PADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		ldr	\rp, =UART_PADDR	@ physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		ldr	\rv, =UART_VADDR	@ virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		.macro	senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		str	\rd, [\rx, #0x40]	@ TXDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		.macro	busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 1002:		ldr	\rd, [\rx, #0x98]	@ SR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		tst	\rd, #1 << 3		@ TXDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		beq	1002b			@ wait until transmit done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		.endm