^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DEBUG_IMX_UART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DEBUG_IMX_UART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IMX1_UART1_BASE_ADDR 0x00206000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX1_UART2_BASE_ADDR 0x00207000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX25_UART1_BASE_ADDR 0x43f90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX25_UART2_BASE_ADDR 0x43f94000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX25_UART3_BASE_ADDR 0x5000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX25_UART4_BASE_ADDR 0x50008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX25_UART5_BASE_ADDR 0x5002c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX27_UART1_BASE_ADDR 0x1000a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX27_UART2_BASE_ADDR 0x1000b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX27_UART3_BASE_ADDR 0x1000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX27_UART4_BASE_ADDR 0x1000d000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX27_UART_BASE_ADDR(n) IMX27_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX27_UART_BASE(n) IMX27_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX31_UART1_BASE_ADDR 0x43f90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX31_UART2_BASE_ADDR 0x43f94000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX31_UART3_BASE_ADDR 0x5000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX31_UART4_BASE_ADDR 0x43fb0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX31_UART5_BASE_ADDR 0x43fb4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX35_UART1_BASE_ADDR 0x43f90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX35_UART2_BASE_ADDR 0x43f94000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX35_UART3_BASE_ADDR 0x5000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX50_UART1_BASE_ADDR 0x53fbc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX50_UART2_BASE_ADDR 0x53fc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX50_UART3_BASE_ADDR 0x5000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX50_UART4_BASE_ADDR 0x53ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX50_UART5_BASE_ADDR 0x63f90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX51_UART1_BASE_ADDR 0x73fbc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX51_UART2_BASE_ADDR 0x73fc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX51_UART3_BASE_ADDR 0x7000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX53_UART1_BASE_ADDR 0x53fbc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX53_UART2_BASE_ADDR 0x53fc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX53_UART3_BASE_ADDR 0x5000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX53_UART4_BASE_ADDR 0x53ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX53_UART5_BASE_ADDR 0x63f90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX6Q_UART1_BASE_ADDR 0x02020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX6Q_UART2_BASE_ADDR 0x021e8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX6Q_UART3_BASE_ADDR 0x021ec000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX6Q_UART4_BASE_ADDR 0x021f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX6Q_UART5_BASE_ADDR 0x021f4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX6SL_UART1_BASE_ADDR 0x02020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX6SL_UART2_BASE_ADDR 0x02024000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX6SL_UART3_BASE_ADDR 0x02034000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX6SL_UART4_BASE_ADDR 0x02038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX6SL_UART5_BASE_ADDR 0x02018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX6SX_UART1_BASE_ADDR 0x02020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX6SX_UART2_BASE_ADDR 0x021e8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX6SX_UART3_BASE_ADDR 0x021ec000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX6SX_UART4_BASE_ADDR 0x021f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX6SX_UART5_BASE_ADDR 0x021f4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX6SX_UART6_BASE_ADDR 0x022a0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX6UL_UART1_BASE_ADDR 0x02020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX6UL_UART2_BASE_ADDR 0x021e8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX6UL_UART3_BASE_ADDR 0x021ec000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX6UL_UART4_BASE_ADDR 0x021f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX6UL_UART5_BASE_ADDR 0x021f4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX6UL_UART6_BASE_ADDR 0x021fc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX6UL_UART7_BASE_ADDR 0x02018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX6UL_UART8_BASE_ADDR 0x02024000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX6UL_UART_BASE_ADDR(n) IMX6UL_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX6UL_UART_BASE(n) IMX6UL_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX7D_UART1_BASE_ADDR 0x30860000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX7D_UART2_BASE_ADDR 0x30890000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX7D_UART3_BASE_ADDR 0x30880000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX7D_UART4_BASE_ADDR 0x30a60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX7D_UART5_BASE_ADDR 0x30a70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX7D_UART6_BASE_ADDR 0x30a80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX7D_UART7_BASE_ADDR 0x30a90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX7D_UART_BASE_ADDR(n) IMX7D_UART##n##_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX7D_UART_BASE(n) IMX7D_UART_BASE_ADDR(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_DEBUG_IMX1_UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #elif defined(CONFIG_DEBUG_IMX25_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #elif defined(CONFIG_DEBUG_IMX27_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #elif defined(CONFIG_DEBUG_IMX31_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #elif defined(CONFIG_DEBUG_IMX35_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #elif defined(CONFIG_DEBUG_IMX50_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #elif defined(CONFIG_DEBUG_IMX51_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #elif defined(CONFIG_DEBUG_IMX53_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #elif defined(CONFIG_DEBUG_IMX6Q_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #elif defined(CONFIG_DEBUG_IMX6SL_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #elif defined(CONFIG_DEBUG_IMX6SX_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #elif defined(CONFIG_DEBUG_IMX6UL_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #elif defined(CONFIG_DEBUG_IMX7D_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif /* __DEBUG_IMX_UART_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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