Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  arch/arm/include/debug/icedcc.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 1994-1999 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		@@ debug using ARM EmbeddedICE DCC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		.macro	senduart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		mcr	p14, 0, \rd, c0, c5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		.macro	busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		mrc	p14, 0, \rx, c0, c1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		tst	\rx, #0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.macro	waituartcts, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		.macro	waituarttxrdy, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		mov	\rd, #0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		subs	\rd, \rd, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		bmi	1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		mrc	p14, 0, \rx, c0, c1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		tst	\rx, #0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		bne	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 1002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #elif defined(CONFIG_CPU_XSCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		.macro	senduart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		mcr	p14, 0, \rd, c8, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.macro	busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		mrc	p14, 0, \rx, c14, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		tst	\rx, #0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		.macro	waituartcts, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		.macro	waituarttxrdy, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		mov	\rd, #0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		subs	\rd, \rd, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		bmi	1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		mrc	p14, 0, \rx, c14, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		tst	\rx, #0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		bne	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 1002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		.macro	senduart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		mcr	p14, 0, \rd, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		.macro	busyuart, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		mrc	p14, 0, \rx, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		tst	\rx, #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		.macro	waituartcts, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		.macro	waituarttxrdy, rd, rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 		mov	\rd, #0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 1001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 		subs	\rd, \rd, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 		bmi	1002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 		mrc	p14, 0, \rx, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 		tst	\rx, #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 		bne	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 1002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif	/* CONFIG_CPU_V6 */