Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *		http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /* pull in the relevant register and map files. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define S3C_ADDR_BASE   0xF6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define S3C_VA_UART	S3C_ADDR_BASE + 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define EXYNOS4_PA_UART	0x13800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define EXYNOS5_PA_UART	0x12C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	/* note, for the boot process to work we have to keep the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	 * virtual address aligned to an 1MiB boundary for the L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	 * mapping the head code makes. We keep the UART virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	 * aligned and add in the offset when we load the value here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.macro addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		mrc	p15, 0, \tmp, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		and	\tmp, \tmp, #0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		teq	\tmp, #0xf0		@@ A15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		beq	100f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		mrc	p15, 0, \tmp, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		and	\tmp, \tmp, #0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		teq	\tmp, #0x100		@@ A15 + A7 but boot to A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 100:		ldreq	\rp, =EXYNOS5_PA_UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		movne	\rp, #EXYNOS4_PA_UART	@@ EXYNOS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		ldr	\rv, =S3C_VA_UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #if CONFIG_DEBUG_S3C_UART != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		add	\rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		add	\rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define fifo_full fifo_full_s5pv210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define fifo_level fifo_level_s5pv210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <debug/samsung.S>