Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2013 Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define UARTn_CMD		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define UARTn_CMD_TXEN			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define	UARTn_STATUS		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define	UARTn_STATUS_TXC		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define	UARTn_STATUS_TXBL		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define	UARTn_TXDATA		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		.macro	addruart, rx, tmp, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		ldr	\rx, =(CONFIG_DEBUG_UART_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		 * enable TX. The driver might disable it to save energy. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		 * don't care about disabling at the end as during debug power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		 * consumption isn't that important.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		ldr	\tmp, =(UARTn_CMD_TXEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		str	\tmp, [\rx, #UARTn_CMD]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		.macro	senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		strb	\rd, [\rx, #UARTn_TXDATA]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 1001:		ldr	\rd, [\rx, #UARTn_STATUS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		tst	\rd, #UARTn_STATUS_TXBL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		.macro	busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 1001:		ldr	\rd, [\rx, UARTn_STATUS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		tst	\rd, #UARTn_STATUS_TXC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		bne	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		.endm