^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Physical register offset and virtual register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_PHYS_BASE 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_PHYS_BASE_V7 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_VIRT_BASE 0xfc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_PHYS_ADDR(x) ((x) + REG_PHYS_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_PHYS_ADDR_V7(x) ((x) + REG_PHYS_BASE_V7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Product id can be read from here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUN_TOP_CTRL_BASE REG_PHYS_ADDR(0x404000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UARTA_3390 REG_PHYS_ADDR(0x40a900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UARTA_7250 REG_PHYS_ADDR(0x40b400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UARTA_7255 REG_PHYS_ADDR(0x40c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UARTA_7260 UARTA_7255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UARTA_7268 UARTA_7255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UARTA_7271 UARTA_7268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UARTA_7216 UARTA_7278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UARTA_72164 UARTA_7278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UARTA_72165 UARTA_7278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UARTA_7364 REG_PHYS_ADDR(0x40b000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UARTA_7366 UARTA_7364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UARTA_74371 REG_PHYS_ADDR(0x406b00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UARTA_7439 REG_PHYS_ADDR(0x40a900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UARTA_7445 REG_PHYS_ADDR(0x40ab00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UART_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define checkuart(rp, rv, family_id, family) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Load family id */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ldr rp, =family_id ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Compare SUN_TOP_CTRL value against it */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cmp rp, rv ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Passed test, load address */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ldreq rp, =UARTA_##family ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Jump to save UART address */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) beq 91f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .macro addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) adr \rp, 99f @ actual addr of 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ldr \rv, [\rp] @ linked addr is stored there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) sub \rv, \rv, \rp @ offset between the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ldr \rp, [\rp, #4] @ linked brcmstb_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) sub \tmp, \rp, \rv @ actual brcmstb_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ldr \rp, [\tmp] @ Load brcmstb_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cmp \rp, #1 @ needs initialization?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bne 100f @ no; go load the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mov \rv, #0 @ yes; record init is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) str \rv, [\tmp]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Check for V7 memory map if B53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mrc p15, 0, \rv, c0, c0, 0 @ get Main ID register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ldr \rp, =ARM_CPU_PART_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) and \rv, \rv, \rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cmp \rv, \rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bne 10f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ands \rv, \rv, #REG_PHYS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ldreq \rp, =SUN_TOP_CTRL_BASE_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Check SUN_TOP_CTRL base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 10: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ldr \rv, [\rp, #0] @ get register contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ARM_BE8( rev \rv, \rv )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) and \rv, \rv, #0xffffff00 @ strip revision bits [7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Chip specific detection starts here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 20: checkuart(\rp, \rv, 0x33900000, 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 21: checkuart(\rp, \rv, 0x72160000, 7216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 22: checkuart(\rp, \rv, 0x07216400, 72164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 23: checkuart(\rp, \rv, 0x07216500, 72165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 24: checkuart(\rp, \rv, 0x72500000, 7250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 25: checkuart(\rp, \rv, 0x72550000, 7255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 26: checkuart(\rp, \rv, 0x72600000, 7260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 27: checkuart(\rp, \rv, 0x72680000, 7268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 28: checkuart(\rp, \rv, 0x72710000, 7271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 29: checkuart(\rp, \rv, 0x72780000, 7278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 30: checkuart(\rp, \rv, 0x73640000, 7364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 31: checkuart(\rp, \rv, 0x73660000, 7366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 32: checkuart(\rp, \rv, 0x07437100, 74371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 33: checkuart(\rp, \rv, 0x74390000, 7439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 34: checkuart(\rp, \rv, 0x74450000, 7445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* No valid UART found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 90: mov \rp, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* fall through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Record whichever UART we chose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 91: str \rp, [\tmp, #4] @ Store in brcmstb_uart_phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cmp \rp, #0 @ Valid UART address?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bne 92f @ Yes, go process it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) b 100f @ Done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 92: and \rv, \rp, #0xffffff @ offset within 16MB section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) add \rv, \rv, #REG_VIRT_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) str \rv, [\tmp, #8] @ Store in brcmstb_uart_virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) b 100f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 99: .word .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .word brcmstb_uart_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .ltorg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Load previously selected UART address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 100: ldr \rp, [\tmp, #4] @ Load brcmstb_uart_phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ldr \rv, [\tmp, #8] @ Load brcmstb_uart_virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .macro store, rd, rx:vararg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ARM_BE8( rev \rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) str \rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .macro load, rd, rx:vararg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ldr \rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ARM_BE8( rev \rd, \rd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .macro senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) store \rd, [\rx, #UART_TX << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .macro busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 1002: load \rd, [\rx, #UART_LSR << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bne 1002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .macro waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .macro waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Storage for the state maintained by the macros above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * That's because this header is included from multiple files, and we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * want a single copy of the data. In particular, the UART probing code above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * assumes it's running using physical addresses. This is true when this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * is included from head.o, but not when included from debug.o. So we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * to share the probe results between the two copies, rather than having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * to re-run the probing again later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * In the decompressor, we put the symbol/storage right here, since common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * isn't included in the decompressor build. This symbol gets put in .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * even though it's really data, since .data is discarded from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * decompressor. Luckily, .text is writeable in the decompressor, unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #if defined(ZIMAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) brcmstb_uart_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Debug UART initialization required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .word 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Debug UART physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Debug UART virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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