Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/include/debug/8250.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 1994-2013 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		.macro	addruart, rp, rv, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		ldr	\rp, =CONFIG_DEBUG_UART_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		ldr	\rv, =CONFIG_DEBUG_UART_VIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifdef CONFIG_DEBUG_UART_8250_WORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		.macro	store, rd, rx:vararg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	 ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		str	\rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	 ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		.macro	load, rd, rx:vararg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		ldr	\rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	ARM_BE8(rev \rd, \rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.macro	store, rd, rx:vararg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		strb	\rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		.macro	load, rd, rx:vararg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		ldrb	\rd, \rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		.macro	senduart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		store	\rd, [\rx, #UART_TX << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		.macro	busyuart,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 1002:		load	\rd, [\rx, #UART_LSR << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		and	\rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		teq	\rd, #UART_LSR_TEMT | UART_LSR_THRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		bne	1002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		.macro	waituarttxrdy,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		.macro	waituartcts,rd,rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 1001:		load	\rd, [\rx, #UART_MSR << UART_SHIFT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		tst	\rd, #UART_MSR_CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		beq	1001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		.endm