^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* sha1-armv7-neon.S - ARM/NEON accelerated SHA-1 transform function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright © 2013-2014 Jussi Kivilinna <jussi.kivilinna@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) .syntax unified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) .fpu neon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Context structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define state_h0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define state_h1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define state_h2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define state_h3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define state_h4 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define K1 0x5A827999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define K2 0x6ED9EBA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define K3 0x8F1BBCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define K4 0xCA62C1D6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .LK_VEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .LK1: .long K1, K1, K1, K1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .LK2: .long K2, K2, K2, K2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .LK3: .long K3, K3, K3, K3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .LK4: .long K4, K4, K4, K4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Register macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RSTATE r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RDATA r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RNBLKS r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ROLDSTACK r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RWK lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define _a r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define _b r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define _c r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define _d r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define _e r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RT0 r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RT1 r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RT2 r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RT3 r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define W0 q0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define W1 q7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define W2 q2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define W3 q3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define W4 q4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define W5 q6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define W6 q5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define W7 q1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define tmp0 q8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define tmp1 q9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define tmp2 q10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define tmp3 q11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define qK1 q12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define qK2 q13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define qK3 q14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define qK4 q15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ARM_LE(code...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ARM_LE(code...) code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Round function macros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WK_offs(i) (((i) & 15) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define _R_F1(a,b,c,d,e,i,pre1,pre2,pre3,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ldr RT3, [sp, WK_offs(i)]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pre1(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bic RT0, d, b; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) add e, e, a, ror #(32 - 5); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) and RT1, c, b; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pre2(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) add RT0, RT0, RT3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) add e, e, RT1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ror b, #(32 - 30); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pre3(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) add e, e, RT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define _R_F2(a,b,c,d,e,i,pre1,pre2,pre3,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ldr RT3, [sp, WK_offs(i)]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pre1(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) eor RT0, d, b; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) add e, e, a, ror #(32 - 5); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) eor RT0, RT0, c; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pre2(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) add e, e, RT3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ror b, #(32 - 30); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pre3(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) add e, e, RT0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define _R_F3(a,b,c,d,e,i,pre1,pre2,pre3,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ldr RT3, [sp, WK_offs(i)]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pre1(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) eor RT0, b, c; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) and RT1, b, c; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) add e, e, a, ror #(32 - 5); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pre2(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) and RT0, RT0, d; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) add RT1, RT1, RT3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) add e, e, RT0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ror b, #(32 - 30); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pre3(i16,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) add e, e, RT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define _R_F4(a,b,c,d,e,i,pre1,pre2,pre3,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) _R_F2(a,b,c,d,e,i,pre1,pre2,pre3,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define _R(a,b,c,d,e,f,i,pre1,pre2,pre3,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) _R_##f(a,b,c,d,e,i,pre1,pre2,pre3,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define R(a,b,c,d,e,f,i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) _R_##f(a,b,c,d,e,i,dummy,dummy,dummy,i16,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define dummy(...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Input expansion macros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /********* Precalc macros for rounds 0-15 *************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define W_PRECALC_00_15() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) add RWK, sp, #(WK_offs(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) vld1.32 {W0, W7}, [RDATA]!; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ARM_LE(vrev32.8 W0, W0; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) vld1.32 {W6, W5}, [RDATA]!; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) vadd.u32 tmp0, W0, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ARM_LE(vrev32.8 W7, W7; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ARM_LE(vrev32.8 W6, W6; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) vadd.u32 tmp1, W7, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ARM_LE(vrev32.8 W5, W5; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) vadd.u32 tmp2, W6, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) vst1.32 {tmp0, tmp1}, [RWK]!; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) vadd.u32 tmp3, W5, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) vst1.32 {tmp2, tmp3}, [RWK]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define WPRECALC_00_15_0(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) vld1.32 {W0, W7}, [RDATA]!; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define WPRECALC_00_15_1(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) add RWK, sp, #(WK_offs(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define WPRECALC_00_15_2(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ARM_LE(vrev32.8 W0, W0; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define WPRECALC_00_15_3(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) vld1.32 {W6, W5}, [RDATA]!; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WPRECALC_00_15_4(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) vadd.u32 tmp0, W0, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define WPRECALC_00_15_5(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ARM_LE(vrev32.8 W7, W7; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define WPRECALC_00_15_6(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ARM_LE(vrev32.8 W6, W6; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define WPRECALC_00_15_7(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) vadd.u32 tmp1, W7, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define WPRECALC_00_15_8(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ARM_LE(vrev32.8 W5, W5; ) /* big => little */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define WPRECALC_00_15_9(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) vadd.u32 tmp2, W6, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define WPRECALC_00_15_10(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) vst1.32 {tmp0, tmp1}, [RWK]!; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define WPRECALC_00_15_11(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) vadd.u32 tmp3, W5, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define WPRECALC_00_15_12(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) vst1.32 {tmp2, tmp3}, [RWK]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /********* Precalc macros for rounds 16-31 ************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define WPRECALC_16_31_0(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) veor tmp0, tmp0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) vext.8 W, W_m16, W_m12, #8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define WPRECALC_16_31_1(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) add RWK, sp, #(WK_offs(i)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) vext.8 tmp0, W_m04, tmp0, #4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define WPRECALC_16_31_2(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) veor tmp0, tmp0, W_m16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) veor.32 W, W, W_m08; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define WPRECALC_16_31_3(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) veor tmp1, tmp1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) veor W, W, tmp0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define WPRECALC_16_31_4(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vshl.u32 tmp0, W, #1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define WPRECALC_16_31_5(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) vext.8 tmp1, tmp1, W, #(16-12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) vshr.u32 W, W, #31; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define WPRECALC_16_31_6(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) vorr tmp0, tmp0, W; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) vshr.u32 W, tmp1, #30; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define WPRECALC_16_31_7(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) vshl.u32 tmp1, tmp1, #2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define WPRECALC_16_31_8(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) veor tmp0, tmp0, W; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define WPRECALC_16_31_9(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) veor W, tmp0, tmp1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define WPRECALC_16_31_10(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) vadd.u32 tmp0, W, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define WPRECALC_16_31_11(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) vst1.32 {tmp0}, [RWK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /********* Precalc macros for rounds 32-79 ************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define WPRECALC_32_79_0(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) veor W, W_m28; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define WPRECALC_32_79_1(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) vext.8 tmp0, W_m08, W_m04, #8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define WPRECALC_32_79_2(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) veor W, W_m16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define WPRECALC_32_79_3(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) veor W, tmp0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define WPRECALC_32_79_4(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) add RWK, sp, #(WK_offs(i&~3)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define WPRECALC_32_79_5(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) vshl.u32 tmp1, W, #2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define WPRECALC_32_79_6(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) vshr.u32 tmp0, W, #30; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define WPRECALC_32_79_7(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) vorr W, tmp0, tmp1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define WPRECALC_32_79_8(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) vadd.u32 tmp0, W, curK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define WPRECALC_32_79_9(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) vst1.32 {tmp0}, [RWK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Transform nblks*64 bytes (nblks*16 32-bit words) at DATA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * sha1_transform_neon (void *ctx, const unsigned char *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * unsigned int nblks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ENTRY(sha1_transform_neon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * r0: ctx, CTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * r1: data (64*nblks bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * r2: nblks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) cmp RNBLKS, #0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) beq .Ldo_nothing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) push {r4-r12, lr};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*vpush {q4-q7};*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) adr RT3, .LK_VEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mov ROLDSTACK, sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Align stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) sub RT0, sp, #(16*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) and RT0, #(~(16-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mov sp, RT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) vld1.32 {qK1-qK2}, [RT3]!; /* Load K1,K2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Get the values of the chaining variables. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ldm RSTATE, {_a-_e};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) vld1.32 {qK3-qK4}, [RT3]; /* Load K3,K4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #undef curK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define curK qK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Precalc 0-15. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) W_PRECALC_00_15();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .Loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Transform 0-15 + Precalc 16-31. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) _R( _a, _b, _c, _d, _e, F1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) WPRECALC_16_31_0, WPRECALC_16_31_1, WPRECALC_16_31_2, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) W4, W5, W6, W7, W0, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) _R( _e, _a, _b, _c, _d, F1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) WPRECALC_16_31_3, WPRECALC_16_31_4, WPRECALC_16_31_5, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) W4, W5, W6, W7, W0, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) _R( _d, _e, _a, _b, _c, F1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) WPRECALC_16_31_6, WPRECALC_16_31_7, WPRECALC_16_31_8, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) W4, W5, W6, W7, W0, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) _R( _c, _d, _e, _a, _b, F1, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) WPRECALC_16_31_9, WPRECALC_16_31_10,WPRECALC_16_31_11,16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) W4, W5, W6, W7, W0, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #undef curK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define curK qK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) _R( _b, _c, _d, _e, _a, F1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) WPRECALC_16_31_0, WPRECALC_16_31_1, WPRECALC_16_31_2, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) W3, W4, W5, W6, W7, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) _R( _a, _b, _c, _d, _e, F1, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) WPRECALC_16_31_3, WPRECALC_16_31_4, WPRECALC_16_31_5, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) W3, W4, W5, W6, W7, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) _R( _e, _a, _b, _c, _d, F1, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) WPRECALC_16_31_6, WPRECALC_16_31_7, WPRECALC_16_31_8, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) W3, W4, W5, W6, W7, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) _R( _d, _e, _a, _b, _c, F1, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) WPRECALC_16_31_9, WPRECALC_16_31_10,WPRECALC_16_31_11,20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) W3, W4, W5, W6, W7, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) _R( _c, _d, _e, _a, _b, F1, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) WPRECALC_16_31_0, WPRECALC_16_31_1, WPRECALC_16_31_2, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) W2, W3, W4, W5, W6, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) _R( _b, _c, _d, _e, _a, F1, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) WPRECALC_16_31_3, WPRECALC_16_31_4, WPRECALC_16_31_5, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) W2, W3, W4, W5, W6, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) _R( _a, _b, _c, _d, _e, F1, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) WPRECALC_16_31_6, WPRECALC_16_31_7, WPRECALC_16_31_8, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) W2, W3, W4, W5, W6, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) _R( _e, _a, _b, _c, _d, F1, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) WPRECALC_16_31_9, WPRECALC_16_31_10,WPRECALC_16_31_11,24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) W2, W3, W4, W5, W6, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) _R( _d, _e, _a, _b, _c, F1, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) WPRECALC_16_31_0, WPRECALC_16_31_1, WPRECALC_16_31_2, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) W1, W2, W3, W4, W5, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) _R( _c, _d, _e, _a, _b, F1, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) WPRECALC_16_31_3, WPRECALC_16_31_4, WPRECALC_16_31_5, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) W1, W2, W3, W4, W5, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) _R( _b, _c, _d, _e, _a, F1, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) WPRECALC_16_31_6, WPRECALC_16_31_7, WPRECALC_16_31_8, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) W1, W2, W3, W4, W5, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) _R( _a, _b, _c, _d, _e, F1, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) WPRECALC_16_31_9, WPRECALC_16_31_10,WPRECALC_16_31_11,28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) W1, W2, W3, W4, W5, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Transform 16-63 + Precalc 32-79. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) _R( _e, _a, _b, _c, _d, F1, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) _R( _d, _e, _a, _b, _c, F1, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) _R( _c, _d, _e, _a, _b, F1, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) _R( _b, _c, _d, _e, _a, F1, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) _R( _a, _b, _c, _d, _e, F2, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) _R( _e, _a, _b, _c, _d, F2, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) _R( _d, _e, _a, _b, _c, F2, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) _R( _c, _d, _e, _a, _b, F2, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #undef curK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define curK qK3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) _R( _b, _c, _d, _e, _a, F2, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) _R( _a, _b, _c, _d, _e, F2, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) _R( _e, _a, _b, _c, _d, F2, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) _R( _d, _e, _a, _b, _c, F2, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) _R( _c, _d, _e, _a, _b, F2, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) _R( _b, _c, _d, _e, _a, F2, 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) _R( _a, _b, _c, _d, _e, F2, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) _R( _e, _a, _b, _c, _d, F2, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) _R( _d, _e, _a, _b, _c, F2, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) W4, W5, W6, W7, W0, W1, W2, W3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) _R( _c, _d, _e, _a, _b, F2, 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) W4, W5, W6, W7, W0, W1, W2, W3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) _R( _b, _c, _d, _e, _a, F2, 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) W4, W5, W6, W7, W0, W1, W2, W3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) _R( _a, _b, _c, _d, _e, F2, 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) W4, W5, W6, W7, W0, W1, W2, W3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) _R( _e, _a, _b, _c, _d, F2, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) W3, W4, W5, W6, W7, W0, W1, W2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) _R( _d, _e, _a, _b, _c, F2, 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) W3, W4, W5, W6, W7, W0, W1, W2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) _R( _c, _d, _e, _a, _b, F2, 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) W3, W4, W5, W6, W7, W0, W1, W2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) _R( _b, _c, _d, _e, _a, F2, 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) W3, W4, W5, W6, W7, W0, W1, W2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) _R( _a, _b, _c, _d, _e, F3, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) W2, W3, W4, W5, W6, W7, W0, W1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) _R( _e, _a, _b, _c, _d, F3, 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) W2, W3, W4, W5, W6, W7, W0, W1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) _R( _d, _e, _a, _b, _c, F3, 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) W2, W3, W4, W5, W6, W7, W0, W1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) _R( _c, _d, _e, _a, _b, F3, 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) W2, W3, W4, W5, W6, W7, W0, W1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #undef curK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define curK qK4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) _R( _b, _c, _d, _e, _a, F3, 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) W1, W2, W3, W4, W5, W6, W7, W0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) _R( _a, _b, _c, _d, _e, F3, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) W1, W2, W3, W4, W5, W6, W7, W0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) _R( _e, _a, _b, _c, _d, F3, 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) W1, W2, W3, W4, W5, W6, W7, W0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) _R( _d, _e, _a, _b, _c, F3, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) W1, W2, W3, W4, W5, W6, W7, W0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) _R( _c, _d, _e, _a, _b, F3, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) _R( _b, _c, _d, _e, _a, F3, 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) _R( _a, _b, _c, _d, _e, F3, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) _R( _e, _a, _b, _c, _d, F3, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) W0, W1, W2, W3, W4, W5, W6, W7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) _R( _d, _e, _a, _b, _c, F3, 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) _R( _c, _d, _e, _a, _b, F3, 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) _R( _b, _c, _d, _e, _a, F3, 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) _R( _a, _b, _c, _d, _e, F3, 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) W7, W0, W1, W2, W3, W4, W5, W6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) _R( _e, _a, _b, _c, _d, F3, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) _R( _d, _e, _a, _b, _c, F3, 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) _R( _c, _d, _e, _a, _b, F3, 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) _R( _b, _c, _d, _e, _a, F3, 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) W6, W7, W0, W1, W2, W3, W4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) subs RNBLKS, #1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) _R( _a, _b, _c, _d, _e, F4, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) WPRECALC_32_79_0, WPRECALC_32_79_1, WPRECALC_32_79_2, 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) _R( _e, _a, _b, _c, _d, F4, 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) WPRECALC_32_79_3, WPRECALC_32_79_4, WPRECALC_32_79_5, 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) _R( _d, _e, _a, _b, _c, F4, 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) WPRECALC_32_79_6, dummy, WPRECALC_32_79_7, 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) _R( _c, _d, _e, _a, _b, F4, 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) WPRECALC_32_79_8, dummy, WPRECALC_32_79_9, 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) W5, W6, W7, W0, W1, W2, W3, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) beq .Lend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Transform 64-79 + Precalc 0-15 of next block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #undef curK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define curK qK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) _R( _b, _c, _d, _e, _a, F4, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) WPRECALC_00_15_0, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) _R( _a, _b, _c, _d, _e, F4, 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) WPRECALC_00_15_1, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) _R( _e, _a, _b, _c, _d, F4, 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) WPRECALC_00_15_2, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) _R( _d, _e, _a, _b, _c, F4, 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) WPRECALC_00_15_3, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) _R( _c, _d, _e, _a, _b, F4, 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dummy, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) _R( _b, _c, _d, _e, _a, F4, 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dummy, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) _R( _a, _b, _c, _d, _e, F4, 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) WPRECALC_00_15_4, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) _R( _e, _a, _b, _c, _d, F4, 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) WPRECALC_00_15_5, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) _R( _d, _e, _a, _b, _c, F4, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dummy, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) _R( _c, _d, _e, _a, _b, F4, 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dummy, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) _R( _b, _c, _d, _e, _a, F4, 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) WPRECALC_00_15_6, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) _R( _a, _b, _c, _d, _e, F4, 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) WPRECALC_00_15_7, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) _R( _e, _a, _b, _c, _d, F4, 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) WPRECALC_00_15_8, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) _R( _d, _e, _a, _b, _c, F4, 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) WPRECALC_00_15_9, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) _R( _c, _d, _e, _a, _b, F4, 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) WPRECALC_00_15_10, dummy, dummy, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) _R( _b, _c, _d, _e, _a, F4, 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) WPRECALC_00_15_11, dummy, WPRECALC_00_15_12, _, _, _, _, _, _, _, _, _ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Update the chaining variables. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ldm RSTATE, {RT0-RT3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) add _a, RT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ldr RT0, [RSTATE, #state_h4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) add _b, RT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) add _c, RT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) add _d, RT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) add _e, RT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) stm RSTATE, {_a-_e};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) b .Loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .Lend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Transform 64-79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) R( _b, _c, _d, _e, _a, F4, 64 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) R( _a, _b, _c, _d, _e, F4, 65 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) R( _e, _a, _b, _c, _d, F4, 66 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) R( _d, _e, _a, _b, _c, F4, 67 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) R( _c, _d, _e, _a, _b, F4, 68 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) R( _b, _c, _d, _e, _a, F4, 69 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) R( _a, _b, _c, _d, _e, F4, 70 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) R( _e, _a, _b, _c, _d, F4, 71 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) R( _d, _e, _a, _b, _c, F4, 72 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) R( _c, _d, _e, _a, _b, F4, 73 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) R( _b, _c, _d, _e, _a, F4, 74 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) R( _a, _b, _c, _d, _e, F4, 75 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) R( _e, _a, _b, _c, _d, F4, 76 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) R( _d, _e, _a, _b, _c, F4, 77 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) R( _c, _d, _e, _a, _b, F4, 78 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) R( _b, _c, _d, _e, _a, F4, 79 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mov sp, ROLDSTACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Update the chaining variables. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ldm RSTATE, {RT0-RT3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) add _a, RT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ldr RT0, [RSTATE, #state_h4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) add _b, RT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) add _c, RT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) add _d, RT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*vpop {q4-q7};*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) add _e, RT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) stm RSTATE, {_a-_e};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pop {r4-r12, pc};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .Ldo_nothing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bx lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ENDPROC(sha1_transform_neon)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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