^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #define __ARM_ARCH__ __LINUX_ARM_ARCH__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) @ SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) @ This code is taken from the OpenSSL project but the author (Andy Polyakov)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) @ has relicensed it under the GPLv2. Therefore this program is free software;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) @ you can redistribute it and/or modify it under the terms of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) @ Public License version 2 as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) @ The original headers, including the original license headers, are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) @ included below for completeness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) @ ====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) @ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) @ project. The module is, however, dual licensed under OpenSSL and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) @ CRYPTOGAMS licenses depending on where you obtain it. For further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) @ details see https://www.openssl.org/~appro/cryptogams/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) @ ====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) @ sha1_block procedure for ARMv4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) @ January 2007.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) @ Size/performance trade-off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) @ ====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) @ impl size in bytes comp cycles[*] measured performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) @ ====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) @ thumb 304 3212 4420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) @ armv4-small 392/+29% 1958/+64% 2250/+96%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) @ armv4-compact 740/+89% 1552/+26% 1840/+22%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) @ full unroll ~5100/+260% ~1260/+4% ~1300/+5%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) @ ====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) @ thumb = same as 'small' but in Thumb instructions[**] and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) @ with recurring code in two private functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) @ small = detached Xload/update, loops are folded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) @ compact = detached Xload/update, 5x unroll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) @ large = interleaved Xload/update, 5x unroll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) @ full unroll = interleaved Xload/update, full unroll, estimated[!];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) @ [*] Manually counted instructions in "grand" loop body. Measured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) @ performance is affected by prologue and epilogue overhead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) @ i-cache availability, branch penalties, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) @ [**] While each Thumb instruction is twice smaller, they are not as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) @ diverse as ARM ones: e.g., there are only two arithmetic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) @ instructions with 3 arguments, no [fixed] rotate, addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) @ modes are limited. As result it takes more instructions to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) @ the same job in Thumb, therefore the code is never twice as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) @ small and always slower.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) @ [***] which is also ~35% better than compiler generated code. Dual-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) @ issue Cortex A8 core was measured to process input block in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) @ ~990 cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) @ August 2010.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) @ Cortex A8 core and in absolute terms ~870 cycles per input block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) @ [or 13.6 cycles per byte].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) @ February 2011.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) @
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) @ Profiler-assisted and platform-specific optimization resulted in 10%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) @ improvement on Cortex A8 core and 12.2 cycles per byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ENTRY(sha1_block_data_order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) stmdb sp!,{r4-r12,lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ldmia r0,{r3,r4,r5,r6,r7}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .Lloop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ldr r8,.LK_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mov r14,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sub sp,sp,#15*4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mov r5,r5,ror#30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mov r6,r6,ror#30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mov r7,r7,ror#30 @ [6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .L_00_15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #if __ARM_ARCH__<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ldrb r10,[r1,#2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ldrb r9,[r1,#3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ldrb r11,[r1,#1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) add r7,r8,r7,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ldrb r12,[r1],#4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) orr r9,r9,r10,lsl#8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) eor r10,r5,r6 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) orr r9,r9,r11,lsl#16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) add r7,r7,r3,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) orr r9,r9,r12,lsl#24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ldr r9,[r1],#4 @ handles unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) add r7,r8,r7,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) eor r10,r5,r6 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) add r7,r7,r3,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef __ARMEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rev r9,r9 @ byte swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) and r10,r4,r10,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) add r7,r7,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) add r7,r7,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #if __ARM_ARCH__<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ldrb r10,[r1,#2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ldrb r9,[r1,#3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ldrb r11,[r1,#1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) add r6,r8,r6,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ldrb r12,[r1],#4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) orr r9,r9,r10,lsl#8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) eor r10,r4,r5 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) orr r9,r9,r11,lsl#16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) add r6,r6,r7,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) orr r9,r9,r12,lsl#24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ldr r9,[r1],#4 @ handles unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) add r6,r8,r6,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) eor r10,r4,r5 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) add r6,r6,r7,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #ifdef __ARMEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rev r9,r9 @ byte swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) and r10,r3,r10,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) add r6,r6,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) add r6,r6,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #if __ARM_ARCH__<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ldrb r10,[r1,#2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ldrb r9,[r1,#3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ldrb r11,[r1,#1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) add r5,r8,r5,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ldrb r12,[r1],#4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) orr r9,r9,r10,lsl#8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) eor r10,r3,r4 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) orr r9,r9,r11,lsl#16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) add r5,r5,r6,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) orr r9,r9,r12,lsl#24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ldr r9,[r1],#4 @ handles unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) add r5,r8,r5,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) eor r10,r3,r4 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) add r5,r5,r6,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifdef __ARMEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rev r9,r9 @ byte swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) and r10,r7,r10,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) add r5,r5,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) add r5,r5,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #if __ARM_ARCH__<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ldrb r10,[r1,#2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ldrb r9,[r1,#3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ldrb r11,[r1,#1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) add r4,r8,r4,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ldrb r12,[r1],#4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) orr r9,r9,r10,lsl#8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) eor r10,r7,r3 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) orr r9,r9,r11,lsl#16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) add r4,r4,r5,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) orr r9,r9,r12,lsl#24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ldr r9,[r1],#4 @ handles unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) add r4,r8,r4,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) eor r10,r7,r3 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) add r4,r4,r5,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef __ARMEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rev r9,r9 @ byte swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) and r10,r6,r10,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) add r4,r4,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) add r4,r4,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #if __ARM_ARCH__<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ldrb r10,[r1,#2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ldrb r9,[r1,#3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ldrb r11,[r1,#1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) add r3,r8,r3,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ldrb r12,[r1],#4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) orr r9,r9,r10,lsl#8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) eor r10,r6,r7 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) orr r9,r9,r11,lsl#16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) add r3,r3,r4,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) orr r9,r9,r12,lsl#24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ldr r9,[r1],#4 @ handles unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) add r3,r8,r3,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) eor r10,r6,r7 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) add r3,r3,r4,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #ifdef __ARMEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rev r9,r9 @ byte swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) and r10,r5,r10,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) add r3,r3,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) add r3,r3,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cmp r14,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bne .L_00_15 @ [((11+4)*5+2)*3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) sub sp,sp,#25*4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #if __ARM_ARCH__<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ldrb r10,[r1,#2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ldrb r9,[r1,#3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ldrb r11,[r1,#1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) add r7,r8,r7,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ldrb r12,[r1],#4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) orr r9,r9,r10,lsl#8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) eor r10,r5,r6 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) orr r9,r9,r11,lsl#16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) add r7,r7,r3,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) orr r9,r9,r12,lsl#24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ldr r9,[r1],#4 @ handles unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) add r7,r8,r7,ror#2 @ E+=K_00_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) eor r10,r5,r6 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) add r7,r7,r3,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifdef __ARMEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rev r9,r9 @ byte swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) and r10,r4,r10,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) add r7,r7,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) add r7,r7,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) add r6,r8,r6,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) eor r10,r4,r5 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) add r6,r6,r7,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) and r10,r3,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) add r6,r6,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) add r6,r6,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) add r5,r8,r5,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) eor r10,r3,r4 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) add r5,r5,r6,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) and r10,r7,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) add r5,r5,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) add r5,r5,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) add r4,r8,r4,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) eor r10,r7,r3 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) add r4,r4,r5,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) and r10,r6,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) add r4,r4,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) add r4,r4,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) add r3,r8,r3,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) eor r10,r6,r7 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) add r3,r3,r4,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) and r10,r5,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) add r3,r3,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) add r3,r3,r10 @ E+=F_00_19(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ldr r8,.LK_20_39 @ [+15+16*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cmn sp,#0 @ [+3], clear carry to denote 20_39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .L_20_39_or_60_79:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) add r7,r8,r7,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) eor r10,r5,r6 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) add r7,r7,r3,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) eor r10,r4,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) add r7,r7,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) add r7,r7,r10 @ E+=F_20_39(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) add r6,r8,r6,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) eor r10,r4,r5 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) add r6,r6,r7,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) eor r10,r3,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) add r6,r6,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) add r6,r6,r10 @ E+=F_20_39(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) add r5,r8,r5,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) eor r10,r3,r4 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) add r5,r5,r6,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) eor r10,r7,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) add r5,r5,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) add r5,r5,r10 @ E+=F_20_39(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) add r4,r8,r4,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) eor r10,r7,r3 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) add r4,r4,r5,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) eor r10,r6,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) add r4,r4,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) add r4,r4,r10 @ E+=F_20_39(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) add r3,r8,r3,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) eor r10,r6,r7 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) add r3,r3,r4,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) eor r10,r5,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) add r3,r3,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) add r3,r3,r10 @ E+=F_20_39(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ARM( teq r14,sp ) @ preserve carry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) THUMB( mov r11,sp )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) THUMB( teq r14,r11 ) @ preserve carry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ldr r8,.LK_40_59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sub sp,sp,#20*4 @ [+2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .L_40_59:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) add r7,r8,r7,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) eor r10,r5,r6 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) add r7,r7,r3,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) and r10,r4,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) and r11,r5,r6 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) add r7,r7,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) add r7,r7,r10 @ E+=F_40_59(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) add r7,r7,r11,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) add r6,r8,r6,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) eor r10,r4,r5 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) add r6,r6,r7,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) and r10,r3,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) and r11,r4,r5 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) add r6,r6,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) add r6,r6,r10 @ E+=F_40_59(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) add r6,r6,r11,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) add r5,r8,r5,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) eor r10,r3,r4 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) add r5,r5,r6,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) and r10,r7,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) and r11,r3,r4 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) add r5,r5,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) add r5,r5,r10 @ E+=F_40_59(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) add r5,r5,r11,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) add r4,r8,r4,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) eor r10,r7,r3 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) add r4,r4,r5,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) and r10,r6,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) and r11,r7,r3 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) add r4,r4,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) add r4,r4,r10 @ E+=F_40_59(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) add r4,r4,r11,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ldr r9,[r14,#15*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ldr r10,[r14,#13*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ldr r11,[r14,#7*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) add r3,r8,r3,ror#2 @ E+=K_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ldr r12,[r14,#2*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) eor r9,r9,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) eor r11,r11,r12 @ 1 cycle stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) eor r10,r6,r7 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mov r9,r9,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) add r3,r3,r4,ror#27 @ E+=ROR(A,27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) eor r9,r9,r11,ror#31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) str r9,[r14,#-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) and r10,r5,r10,ror#2 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) and r11,r6,r7 @ F_xx_xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) add r3,r3,r9 @ E+=X[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) add r3,r3,r10 @ E+=F_40_59(B,C,D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) add r3,r3,r11,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cmp r14,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bne .L_40_59 @ [+((12+5)*5+2)*4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ldr r8,.LK_60_79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sub sp,sp,#20*4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cmp sp,#0 @ set carry to denote 60_79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) b .L_20_39_or_60_79 @ [+4], spare 300 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .L_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) add sp,sp,#80*4 @ "deallocate" stack frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ldmia r0,{r8,r9,r10,r11,r12}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) add r3,r8,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) add r4,r9,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) add r5,r10,r5,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) add r6,r11,r6,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) add r7,r12,r7,ror#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) stmia r0,{r3,r4,r5,r6,r7}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) teq r1,r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) bne .Lloop @ [+18], total 1307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ldmia sp!,{r4-r12,pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .LK_00_19: .word 0x5a827999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .LK_20_39: .word 0x6ed9eba1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .LK_40_59: .word 0x8f1bbcdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .LK_60_79: .word 0xca62c1d6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ENDPROC(sha1_block_data_order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .align 2
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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